Searched refs:CCs (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 669 std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID); in InitCmpLibcallCCs()
670 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
671 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
674 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
675 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
678 CCs[RTLIB::OGE_F32] = ISD::SETGE; in InitCmpLibcallCCs()
679 CCs[RTLIB::OGE_F64] = ISD::SETGE; in InitCmpLibcallCCs()
682 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
683 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
694 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CallingConvEmitter.cpp | 44 std::vector<Record*> CCs = Records.getAllDerivedDefinitions("CallingConv"); in run() local
50 for (Record *CC : CCs) { in run()
69 for (Record *CC : CCs) { in run()
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| /llvm-project-15.0.7/clang/lib/Basic/ |
| H A D | Targets.cpp | 94 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; in addCygMingDefines() local
95 for (const char *CC : CCs) { in addCygMingDefines()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2404 void setCondCodeAction(ArrayRef<ISD::CondCode> CCs, MVT VT, in setCondCodeAction() argument
2406 for (auto CC : CCs) { in setCondCodeAction()
2418 void setCondCodeAction(ArrayRef<ISD::CondCode> CCs, ArrayRef<MVT> VTs, in setCondCodeAction() argument
2421 setCondCodeAction(CCs, VT, Action); in setCondCodeAction()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 117 // logic. FIXME: See if the logic can be simplified with use of CCs.
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-ccmp.ll | 850 ; Test the IR CCs that expand to two cond codes.
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