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Searched refs:CCState (Results 1 – 25 of 64) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallingConv.h22 CCState &State);
25 CCState &State);
28 CCState &State);
31 CCState &State);
34 CCState &State);
37 ISD::ArgFlagsTy ArgFlags, CCState &State);
40 CCState &State);
43 CCState &State);
46 CCState &State);
49 CCState &State);
H A DARMCallingConv.cpp23 CCState &State, bool CanFail) { in f64AssignAPCS()
52 CCState &State) { in CC_ARM_APCS_Custom_f64()
64 CCState &State, bool CanFail) { in f64AssignAAPCS()
105 CCState &State) { in CC_ARM_AAPCS_Custom_f64()
115 CCValAssign::LocInfo LocInfo, CCState &State) { in f64RetAssign()
137 CCState &State) { in RetCC_ARM_APCS_Custom_f64()
148 CCState &State) { in RetCC_ARM_AAPCS_Custom_f64()
173 CCState &State) { in CC_ARM_AAPCS_Custom_Aggregate()
288 CCValAssign::LocInfo LocInfo, CCState &State, in CustomAssignInRegList()
300 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_ARM_AAPCS_Custom_f16()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.h21 CCState &State);
24 ISD::ArgFlagsTy ArgFlags, CCState &State);
27 ISD::ArgFlagsTy ArgFlags, CCState &State);
30 ISD::ArgFlagsTy ArgFlags, CCState &State);
33 ISD::ArgFlagsTy ArgFlags, CCState &State);
36 ISD::ArgFlagsTy ArgFlags, CCState &State);
39 ISD::ArgFlagsTy ArgFlags, CCState &State);
42 CCState &State);
45 CCState &State);
48 ISD::ArgFlagsTy ArgFlags, CCState &State);
H A DAArch64CallingConvention.cpp44 CCState &State, Align SlotAlign) { in finishStackBlock()
106 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_AArch64_Custom_Stack_Block()
125 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_AArch64_Custom_Block()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCallingConvLower.cpp28 CCState::CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &mf, in CCState() function in CCState
42 void CCState::HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, in HandleByVal()
59 void CCState::MarkAllocated(MCPhysReg Reg) { in MarkAllocated()
64 void CCState::MarkUnallocated(MCPhysReg Reg) { in MarkUnallocated()
69 bool CCState::IsShadowAllocatedReg(MCRegister Reg) const { in IsShadowAllocatedReg()
175 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
185 void CCState::ensureMaxAlignment(Align Alignment) { in ensureMaxAlignment()
237 void CCState::analyzeMustTailForwardedRegisters( in analyzeMustTailForwardedRegisters()
258 bool CCState::resultsCompatible(CallingConv::ID CalleeCC, in resultsCompatible()
266 CCState CCInfo1(CalleeCC, false, MF, RVLocs1, C); in resultsCompatible()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.h24 CCState &State);
27 CCState &State);
30 CCState &State);
33 CCState &State);
36 CCState &State);
39 CCState &State);
42 ISD::ArgFlagsTy ArgFlags, CCState &State);
H A DPPCCCState.h19 class PPCCCState : public CCState {
35 : CCState(CC, isVarArg, MF, locs, C) {} in PPCCCState()
41 class AIXCCState : public CCState {
48 : CCState(CC, IsVarArg, MF, Locs, C) {} in AIXCCState()
54 CCState::AnalyzeFormalArguments(Ins, Fn); in AnalyzeFormalArguments()
65 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
H A DPPCCallingConv.cpp17 CCState &) { in CC_PPC_AnyReg_Error() argument
27 CCState &State) { in CC_PPC32_SVR4_Custom_Dummy()
35 CCState &State) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
60 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
85 CCState &State) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
113 CCState &State) { in CC_PPC32_SPE_CustomSplitFP64()
142 CCState &State) { in CC_PPC32_SPE_RetF64()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h32 class SystemZCCState : public CCState {
49 : CCState(CC, isVarArg, MF, locs, C) {} in SystemZCCState()
62 CCState::AnalyzeFormalArguments(Ins, Fn); in AnalyzeFormalArguments()
76 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
98 CCState &State) { in CC_SystemZ_I128Indirect()
147 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_XPLINK64_Shadow_Reg()
171 CCState &State) { in CC_XPLINK64_Allocate128BitVararg()
207 CCState &) { in RetCC_SystemZ_Error() argument
212 ISD::ArgFlagsTy &, CCState &) { in CC_SystemZ_Error() argument
218 CCState &) { in CC_SystemZ_GHC_Error() argument
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCCState.h20 class MipsCCState : public CCState {
101 : CCState(CC, isVarArg, MF, locs, C), SpecialCallingConv(SpecialCC) {} in CCState() function
119 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
142 CCState::AnalyzeFormalArguments(Ins, Fn); in AnalyzeFormalArguments()
165 CCState::AnalyzeCallResult(Ins, Fn); in AnalyzeCallResult()
180 CCState::AnalyzeReturn(Outs, Fn); in AnalyzeReturn()
187 bool Return = CCState::CheckReturn(ArgsFlags, Fn); in CheckReturn()
H A DMips16ISelLowering.h35 const CCState &CCInfo, unsigned NextStackOffset,
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallingConv.cpp30 CCState &State) { in CC_X86_32_RegCall_Assign2Regs()
94 CCState &State) { in CC_X86_VectorCallAssignRegister()
130 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_X86_64_VectorCall()
190 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_X86_32_VectorCall()
230 CCState &) { in CC_X86_AnyReg_Error() argument
239 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_X86_32_MCUInReg()
299 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_X86_Intr()
335 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_X86_64_Pointer()
H A DX86CallingConv.h25 CCState &State);
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kCallingConv.h27 struct M68kCCState : public CCState {
33 : CCState(CC, IsVarArg, MF, Locs, C), ArgTypeList(ArgTypes) {} in M68kCCState()
40 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_M68k_Any_AssignToReg()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h90 CCState &State);
92 void analyzeInputArgs(CCState &CCInfo,
95 void analyzeOutputArgs(CCState &CCInfo,
H A DLoongArchISelLowering.cpp830 CCValAssign::LocInfo LocInfo, CCState &State) { in CC_LoongArch()
850 CCState &CCInfo, const SmallVectorImpl<ISD::InputArg> &Ins, in analyzeInputArgs()
864 CCState &CCInfo, const SmallVectorImpl<ISD::OutputArg> &Outs, in analyzeOutputArgs()
907 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerFormalArguments()
941 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); in LowerCall()
1026 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerCall()
1060 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.h27 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_CSKY_ABIV2_SOFT_64()
46 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in Ret_CSKY_ABIV2_SOFT_64()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h184 ISD::ArgFlagsTy Flags, CCState &State) { in assignArg()
386 CCState &CCInfo) const;
403 CCState &CCState,
470 bool checkReturn(CCState &CCInfo, SmallVectorImpl<BaseArgInfo> &Outs,
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h25 class CCState; variable
177 ISD::ArgFlagsTy ArgFlags, CCState &State);
184 ISD::ArgFlagsTy &ArgFlags, CCState &State);
189 class CCState {
248 CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h356 CCState &CCInfo,
496 void allocateHSAUserSGPRs(CCState &CCInfo,
501 void allocateSystemSGPRs(CCState &CCInfo,
507 void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
512 CCState &CCInfo,
517 void allocateSpecialInputVGPRs(CCState &CCInfo,
521 void allocateSpecialInputVGPRsFixed(CCState &CCInfo,
H A DAMDGPUCallLowering.cpp276 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, in canLowerReturn()
439 static void allocateHSAUserSGPRs(CCState &CCInfo, in allocateHSAUserSGPRs()
504 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); in lowerFormalArgumentsKernel()
588 CCState CCInfo(CC, F.isVarArg(), MF, ArgLocs, F.getContext()); in lowerFormalArguments()
740 CCState &CCInfo, in passSpecialInputs()
1035 CCState OutInfo(CalleeCC, false, MF, OutLocs, CallerF.getContext()); in areCalleeOutgoingArgsTailCallable()
1207 CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext()); in lowerTailCall()
1233 CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext()); in lowerTailCall()
1353 CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext()); in lowerCall()
H A DAMDGPUCallLowering.h55 CCState &CCInfo,
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h610 ISD::ArgFlagsTy ArgFlags, CCState &State,
615 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
618 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
699 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp440 static void AnalyzeVarArgs(CCState &State, in AnalyzeVarArgs()
445 static void AnalyzeVarArgs(CCState &State, in AnalyzeVarArgs()
455 static void AnalyzeArguments(CCState &State, in AnalyzeArguments()
549 static void AnalyzeRetResult(CCState &State, in AnalyzeRetResult()
554 static void AnalyzeRetResult(CCState &State, in AnalyzeRetResult()
560 static void AnalyzeReturnValues(CCState &State, in AnalyzeReturnValues()
628 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCArguments()
730 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
751 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
813 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCCCCallTo()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp88 CCState &State) override { in assignArg()
114 CCState &State) override { in assignArg()
476 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, in canLowerReturn()
500 CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs, in handleMustTailForwardedRegisters()
754 CCState OutInfo(CalleeCC, false, MF, OutLocs, Ctx); in areCalleeOutgoingArgsTailCallable()
1002 CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext()); in lowerTailCall()

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