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Searched refs:CCR (Results 1 – 25 of 40) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrControl.td95 let Uses = [CCR] in {
163 let isBranch = 1, isTerminator = 1, Uses = [CCR] in
197 def : Pat<(MxBrCond bb:$target, !cast<PatLeaf>("MxCOND"#cc), CCR),
314 let Uses = [CCR], Defs = [CCR], isPseudo = 1 in {
324 } // Uses = [CCR], Defs = [CCR], isPseudo = 1
330 def : Pat<(i16 (sext (i8 (MxSetCC_C MxCONDcs, CCR)))), (SETCS_C16d)>;
337 def : Pat<(and (i8 (MxSetCC_C MxCONDcs, CCR)), 1), (SETd8cs)>;
340 def : Pat<(add (and (i8 (MxSetCC_C MxCONDcs, CCR)), 1), MxDRD8:$op),
346 def : Pat<(sub MxDRD8:$op, (and (i8 (MxSetCC_C MxCONDcs, CCR)), 1)),
352 def : Pat<(sub MxDRD8:$op, (i8 (MxSetCC_C MxCONDcs, CCR))),
[all …]
H A DM68kInstrBits.td60 let Defs = [CCR] in {
63 [(set CCR, (MxBtst TYPE.VT:$dst, TYPE.VT:$bitno))]> {
69 [(set CCR, (MxBtst TYPE.VT:$dst, TYPE.IPat:$bitno))]> {
76 [(set CCR, (MxBtst (TYPE.Load MEMPat:$dst), TYPE.VT:$bitno))]> {
83 [(set CCR, (MxBtst (TYPE.Load MEMPat:$dst), TYPE.IPat:$bitno))]> {
86 } // Defs = [CCR]
H A DM68kInstrArithmetic.td56 let Defs = [CCR] in {
193 } // Defs = [CCR]
314 let Uses = [CCR], Defs = [CCR] in {
389 let Defs = [CCR] in {
475 } // let Defs = [CCR]
529 let Defs = [CCR] in
570 let Defs = [CCR] in {
599 } // Defs = [CCR]
751 let Defs = [CCR] in {
767 let Uses = [CCR] in {
[all …]
H A DM68kInstrCompiler.td57 let usesCustomInserter = 1, Uses = [CCR] in
61 (TYPE.VT (MxCmov TYPE.VT:$t, TYPE.VT:$f, imm:$cond, CCR)))]>;
76 // sub / add which can clobber CCR.
77 let Defs = [SP, CCR], Uses = [SP] in {
123 let Defs = [SP, CCR], Uses = [SP] in
H A DM68kInstrInfo.td37 /* CCR */ SDTCisVT<1, i8>,
41 // RES, CCR <- op LHS, RHS
44 /* CCR */ SDTCisVT<1, i8>,
49 // RES, CCR <- op LHS, RHS, CCR
52 /* CCR */ SDTCisVT<1, i8>,
62 /* CCR */ SDTCisVT<1, i8>,
68 /* CCR */ SDTCisVT<0, i8>,
76 /* CCR */ SDTCisVT<4, i8>
82 /* CCR */ SDTCisVT<2, i8>
88 /* CCR */ SDTCisVT<2, i8>
[all …]
H A DM68kInstrData.td105 let Defs = [CCR] in
340 // MOVE to/from SR/CCR
342 // A special care must be taken working with to/from CCR since it is basically
344 // instructions. Plus the original M68000 does not support moves from CCR. So in
345 // order to use CCR effectively one MUST use proper byte-size pseudo instructi-
355 let Defs = [CCR] in
378 /// Move from CCR
385 let Uses = [CCR] in {
403 } // let Uses = [CCR]
464 let Defs = [CCR] in {
H A DM68kInstrShiftRotate.td77 let Defs = [CCR] in {
89 } // Defs = [CCR]
H A DM68kISelLowering.cpp2925 if (mi.readsRegister(M68k::CCR)) in checkAndUpdateCCRKill()
2927 if (mi.definesRegister(M68k::CCR)) in checkAndUpdateCCRKill()
2935 if (SBB->isLiveIn(M68k::CCR)) in checkAndUpdateCCRKill()
2940 SelectItr->addRegisterKilled(M68k::CCR, TRI); in checkAndUpdateCCRKill()
3040 Jcc1MBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
3055 Copy0MBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
3056 SinkMBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
3360 if (CCR.getOpcode() == M68kISD::ADD) { in combineCarryThroughADD()
3362 SDValue Carry = CCR.getOperand(0); in combineCarryThroughADD()
3399 SDValue CCR = N->getOperand(1); in combineM68kSetCC() local
[all …]
H A DM68kRegisterInfo.td76 def CCR : MxPseudoReg<"ccr">;
107 def CCRC : MxRegClass<[i8], 16, (add CCR)>;
H A DM68kInstrInfo.cpp669 bool FromCCR = SrcReg == M68k::CCR; in copyPhysReg()
671 bool ToCCR = DstReg == M68k::CCR; in copyPhysReg()
/llvm-project-15.0.7/clang/lib/AST/
H A DComparisonCategories.cpp204 using CCR = ComparisonCategoryResult; in getPossibleResultsForType() typedef
205 std::vector<CCR> Values; in getPossibleResultsForType()
208 Values.push_back(IsStrong ? CCR::Equal : CCR::Equivalent); in getPossibleResultsForType()
209 Values.push_back(CCR::Less); in getPossibleResultsForType()
210 Values.push_back(CCR::Greater); in getPossibleResultsForType()
212 Values.push_back(CCR::Unordered); in getPossibleResultsForType()
/llvm-project-15.0.7/clang/include/clang/AST/
H A DComparisonCategories.h152 using CCR = ComparisonCategoryResult; in makeWeakResult() local
153 if (!isStrong() && Res == CCR::Equal) in makeWeakResult()
154 return CCR::Equivalent; in makeWeakResult()
H A DExpr.h4979 const_child_range CCR = const_cast<const InitListExpr *>(this)->children(); in children() local
4980 return child_range(cast_away_const(CCR.begin()), in children()
4981 cast_away_const(CCR.end())); in children()
6208 const_child_range CCR = in children() local
6210 return child_range(cast_away_const(CCR.begin()), in children()
6211 cast_away_const(CCR.end())); in children()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterBanks.td19 def CCRegBank : RegisterBank<"CC", [CCR]>;
H A DAArch64GenRegisterBankInfo.def217 PMI_None, // CCR
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td60 def CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> {
/llvm-project-15.0.7/llvm/lib/Target/M68k/AsmParser/
H A DM68kAsmParser.cpp252 case M68k::CCR: in getRegisterIndex()
494 case M68k::CCR: in checkRegisterClass()
584 RegNo = M68k::CCR; in parseRegisterName()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td296 def CCR : Rs<7, "ccr", ["s7"]>, DwarfRegNum<[151]>;
377 def S7_6 : Rss<6, "s7:6", [SSR, CCR], ["ccr:ssr"]>, DwarfRegNum<[150]>;
599 SSR, CCR, HTID, BADVA, IMASK,
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td421 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
654 def CCROpnd : RegisterOperand<CCR> {
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td223 def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)> {
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4947 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO() local
5127 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
5210 ARMcc, CCR, Cmp); in getCMOV()
5526 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
5747 Chain, Dest, ARMcc, CCR, Cmp); in LowerBR_CC()
5762 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
5764 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; in LowerBR_CC()
6293 ARMcc, CCR, CmpLo); in LowerShiftRightParts()
6303 ARMcc, CCR, CmpHi); in LowerShiftRightParts()
6336 ARMcc, CCR, CmpHi); in LowerShiftLeftParts()
[all …]
H A DARMISelLowering.h951 SDValue ARMcc, SDValue CCR, SDValue Cmp,
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DGMIR.rst127 point and also for the NEON vector instruction set. The third is CCR and
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td578 def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {
650 def FixedRegisters : RegisterCategory<[DEBUG_REG, CONTROL_REG, CCR, FPCCR,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td322 def CCR : RegisterClass<"SystemZ", [i32], 32, (add CC)>;

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