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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dstore-prepostinc.mir48 BX_RET 14 /* CC::al */, $noreg, implicit $r0
69 BX_RET 14 /* CC::al */, $noreg, implicit $r0
90 BX_RET 14 /* CC::al */, $noreg, implicit $r0
111 BX_RET 14 /* CC::al */, $noreg, implicit $r0
132 BX_RET 14 /* CC::al */, $noreg, implicit $r0
153 BX_RET 14 /* CC::al */, $noreg, implicit $r0
174 BX_RET 14 /* CC::al */, $noreg, implicit $r0
195 BX_RET 14 /* CC::al */, $noreg, implicit $r0
216 BX_RET 14 /* CC::al */, $noreg, implicit $r0
237 BX_RET 14 /* CC::al */, $noreg, implicit $r0
[all …]
H A Dmachine-outliner-lr-regsave.mir41 ; CHECK: $r2 = MOVr $lr, 14 /* CC::al */, $noreg, $noreg
42 ; CHECK: BX_RET 14 /* CC::al */, $noreg
108 ; CHECK: $r2 = tMOVr $lr, 14 /* CC::al */, $noreg
109 ; CHECK: tBX_RET 14 /* CC::al */, $noreg
156 ; CHECK: tBX_RET 14 /* CC::al */, $noreg
161 ; CHECK: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
162 ; CHECK: $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
163 ; CHECK: $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
164 ; CHECK: $r3 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
165 ; CHECK: $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
[all …]
H A Dmachine-outliner-default.mir36 ; CHECK: $r2 = MOVr $lr, 14 /* CC::al */, $noreg, $noreg
37 ; CHECK: BX_RET 14 /* CC::al */, $noreg
90 ; CHECK: $r2 = tMOVr $lr, 14 /* CC::al */, $noreg
91 ; CHECK: tBX_RET 14 /* CC::al */, $noreg
118 ; CHECK: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
119 ; CHECK: $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
120 ; CHECK: $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
121 ; CHECK: $r3 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
122 ; CHECK: $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
124 ; CHECK: MOVPCLR 14 /* CC::al */, $noreg
[all …]
H A Dmachine-outliner-thunk.ll36 ; THUMB-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
47 ; MACHO-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
78 ; THUMB-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
99 ; ARM: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
100 ; ARM-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
101 ; ARM-NEXT: $r2 = MOVi 3, 14 /* CC::al */, $noreg, $noreg
102 ; ARM-NEXT: $r3 = MOVi 4, 14 /* CC::al */, $noreg, $noreg
108 ; THUMB: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
109 ; THUMB-NEXT: $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
110 ; THUMB-NEXT: $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
[all …]
H A Dstack_frame_offset.mir70 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 2, 14 /* CC::al */, $noreg
75 ; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 2, 14 /* CC::al */, $noreg
78 renamable $r0 = t2ADDri %stack.0.a, 0, 14 /* CC::al */, $noreg, $noreg
82 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
122 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 2, 14 /* CC::al */, $noreg
127 ; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 2, 14 /* CC::al */, $noreg
130 renamable $r0 = t2ADDri %stack.0.a, 0, 14 /* CC::al */, $noreg, $noreg
134 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
174 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 2, 14 /* CC::al */, $noreg
182 renamable $r0 = t2ADDri %stack.0.a, 0, 14 /* CC::al */, $noreg, $noreg
[all …]
H A Dmachine-outliner-stack-fixup-thumb.mir22 ;CHECK: $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg
24 ;CHECK-NEXT: $r0 = t2LDRi12 $sp, 4088, 14 /* CC::al */, $noreg
52 ;CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg
54 ;CHECK-NEXT: t2STRHT $r0, $sp, 248, 14 /* CC::al */, $noreg
82 ;CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg
112 ;CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg
147 ;CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg
188 ;CHECK-NEXT: $r1 = t2LDREX $sp, 2, 14 /* CC::al */, $noreg
198 ;CHECK-NEXT: t2STRHT $r0, $sp, 8, 14 /* CC::al */, $noreg
228 ;CHECK-NEXT: tSTRspi $r0, $sp, 2, 14 /* CC::al */, $noreg
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dstore-prepostinc.mir63 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
85 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
107 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
129 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
152 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
174 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
197 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
220 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
243 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
266 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
[all …]
H A Dscavenge-lr.mir134 $q1 = VMULfq $q12, killed $q8, 14 /* CC::al */, $noreg
139 $q14 = VMULfq $q15, $q10, 14 /* CC::al */, $noreg
142 $q8 = VMULfq $q14, $q13, 14 /* CC::al */, $noreg
143 $r4 = t2SUBri $r0, 96, 14 /* CC::al */, $noreg, $noreg
145 $q8 = VMULfq killed $q8, $q6, 14 /* CC::al */, $noreg
154 $r7 = t2SUBri $r0, 64, 14 /* CC::al */, $noreg, $noreg
165 $q11 = VMULfq $q10, $q0, 14 /* CC::al */, $noreg
173 $q7 = VMULfq $q4, $q11, 14 /* CC::al */, $noreg
176 $q8 = VMULfq $q7, $q3, 14 /* CC::al */, $noreg
201 $q9 = VMULfq $q8, killed $q9, 14 /* CC::al */, $noreg
[all …]
H A Dbti-jump-table.mir56 ; CHECK: t2Bcc %bb.3, 8 /* CC::hi */, killed $cpsr
67 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
74 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
78 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
82 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
89 t2Bcc %bb.5, 8 /* CC::hi */, killed $cpsr
95 renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
102 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
110 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
114 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
[all …]
H A Dmve-wls-block-placement.mir115 t2B %bb.1, 14 /* CC::al */, $noreg
172 t2B %bb.1, 14 /* CC::al */, $noreg
241 t2B %bb.5, 14 /* CC::al */, $noreg
248 t2B %bb.4, 14 /* CC::al */, $noreg
255 t2B %bb.1, 14 /* CC::al */, $noreg
262 t2B %bb.3, 14 /* CC::al */, $noreg
341 t2B %bb.3, 14 /* CC::al */, $noreg
348 t2B %bb.3, 14 /* CC::al */, $noreg
508 t2B %bb.2, 14 /* CC::al */, $noreg
533 t2B %bb.4, 14 /* CC::al */, $noreg
[all …]
H A Dswp-fixedii.mir62 ; CHECK-NEXT: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr
68 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg
91 ; CHECK-NEXT: t2Bcc %bb.9, 0 /* CC::eq */, $cpsr
92 ; CHECK-NEXT: t2B %bb.6, 14 /* CC::al */, $noreg
106 ; CHECK-NEXT: t2Bcc %bb.8, 0 /* CC::eq */, $cpsr
160 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr
166 t2B %bb.3, 14 /* CC::al */, $noreg
194 t2Bcc %bb.2, 1 /* CC::ne */, $cpsr
195 t2B %bb.3, 14 /* CC::al */, $noreg
199 %24:gpr = VMOVRS %10, 14 /* CC::al */, $noreg
[all …]
H A Dswp-exitbranchdir.mir62 ; CHECK-NEXT: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr
68 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg
91 ; CHECK-NEXT: t2Bcc %bb.9, 0 /* CC::eq */, $cpsr
92 ; CHECK-NEXT: t2B %bb.6, 14 /* CC::al */, $noreg
106 ; CHECK-NEXT: t2Bcc %bb.8, 0 /* CC::eq */, $cpsr
160 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr
166 t2B %bb.3, 14 /* CC::al */, $noreg
194 t2Bcc %bb.3, 0 /* CC::eq */, $cpsr
195 t2B %bb.2, 14 /* CC::al */, $noreg
199 %24:gpr = VMOVRS %10, 14 /* CC::al */, $noreg
[all …]
H A Dconstant-islands-cbzundef.mir23 ; CHECK: renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
30 ; CHECK: $r0 = t2MOVi16 target-flags(arm-lo16) @b, 14 /* CC::al */, $noreg
36 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit undef $r0
40 renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
41 tCMPi8 killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
42 t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
47 tCMPi8 undef renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
48 t2Bcc %bb.3, 0 /* CC::eq */, killed $cpsr
53 $r0 = t2MOVi16 target-flags(arm-lo16) @b, 14 /* CC::al */, $noreg
54 $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @b, 14 /* CC::al */, $noreg
[all …]
H A Dconstant-islands-ldrsb.mir24 $sp = frame-setup tSUBspi $sp, 3, 14 /* CC::al */, $noreg
27 renamable $r1 = tMOVr $sp, 14 /* CC::al */, $noreg
29 $r1 = t2MOVi16 target-flags(arm-lo16) @t2LDRSBpci, 14 /* CC::al */, $noreg
31 $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @t2LDRSBpci, 14 /* CC::al */, $noreg
33 $sp = frame-destroy tADDspi $sp, 3, 14 /* CC::al */, $noreg
34 tBX_RET 14 /* CC::al */, $noreg
47 $sp = frame-setup tSUBspi $sp, 3, 14 /* CC::al */, $noreg
50 renamable $r1 = tMOVr $sp, 14 /* CC::al */, $noreg
52 $r1 = t2MOVi16 target-flags(arm-lo16) @t2LDRSHpci, 14 /* CC::al */, $noreg
56 $sp = frame-destroy tADDspi $sp, 3, 14 /* CC::al */, $noreg
[all …]
H A Dswp-fixedii-le.mir62 ; CHECK-NEXT: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr
68 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg
94 ; CHECK-NEXT: t2Bcc %bb.7, 0 /* CC::eq */, $cpsr
95 ; CHECK-NEXT: t2B %bb.6, 14 /* CC::al */, $noreg
117 ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg
125 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg
140 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr
146 t2B %bb.3, 14 /* CC::al */, $noreg
177 t2B %bb.3, 14 /* CC::al */, $noreg
181 %24:gpr = VMOVRS %10, 14 /* CC::al */, $noreg
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Darm-instruction-select-cmp.mir77 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
107 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
137 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
167 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
197 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
227 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
257 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
287 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
317 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
347 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
[all …]
H A Dthumb-instruction-select-cmp.mir32 ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
37 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
67 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
97 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
127 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
157 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
187 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
217 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
247 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
277 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
[all …]
H A Darm-call-lowering.ll15 ; NOV4T: MOVPCLR 14 /* CC::al */, $noreg
20 ; V4T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
22 ; V4T: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
23 ; V4T: BX_RET 14 /* CC::al */, $noreg
30 ; V5T: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
31 ; V5T: BX_RET 14 /* CC::al */, $noreg
39 ; THUMB: tBX_RET 14 /* CC::al */, $noreg
53 ; NOV4T: MOVPCLR 14 /* CC::al */, $noreg
59 ; V4T: BX_RET 14 /* CC::al */, $noreg
65 ; V5T: BX_RET 14 /* CC::al */, $noreg
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dspillingmove.mir95 tBcc %bb.5, 11 /* CC::lt */, killed $cpsr
116 $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
117 $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
132 tB %bb.4, 14 /* CC::al */, $noreg
141 tBcc %bb.2, 1 /* CC::ne */, killed $cpsr
248 $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
249 $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
265 tB %bb.4, 14 /* CC::al */, $noreg
274 tBcc %bb.2, 1 /* CC::ne */, killed $cpsr
384 $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
[all …]
H A Dno-dec-reorder.mir123 ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
143 ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
154 ; CHECK: tB %bb.7, 14 /* CC::al */, $noreg
167 ; CHECK: tB %bb.9, 14 /* CC::al */, $noreg
176 ; CHECK: tB %bb.8, 14 /* CC::al */, $noreg
193 t2B %bb.3, 14 /* CC::al */, $noreg
208 t2Bcc %bb.9, 0 /* CC::eq */, killed $cpsr
219 t2B %bb.4, 14 /* CC::al */, $noreg
234 t2B %bb.7, 14 /* CC::al */, $noreg
251 t2B %bb.6, 14 /* CC::al */, $noreg
[all …]
H A Dvector_spill_in_loop.mir26 ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
59 $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
60 $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
61 $r9 = tMOVr $r3, 14 /* CC::al */, $noreg
81 tB %bb.2, 14 /* CC::al */, $noreg
94 tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
155 $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
156 $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
157 $r9 = tMOVr $r3, 14 /* CC::al */, $noreg
177 tB %bb.2, 14 /* CC::al */, $noreg
[all …]
H A Dbiquad-cascade-default.mir225 ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
243 ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
317 tB %bb.2, 14 /* CC::al */, $noreg
328 $r1 = tMOVr $r12, 14 /* CC::al */, $noreg
329 tBcc %bb.6, 0 /* CC::eq */, killed $cpsr
338 tB %bb.3, 14 /* CC::al */, $noreg
370 $lr = tMOVr $r8, 14 /* CC::al */, $noreg
376 $r0 = tMOVr $r7, 14 /* CC::al */, $noreg
377 $r4 = tMOVr $r5, 14 /* CC::al */, $noreg
379 tB %bb.5, 14 /* CC::al */, $noreg
[all …]
H A Dno-dec-cbnz.mir116 ; CHECK-LOB: tBcc %bb.5, 13 /* CC::le */, killed $cpsr
153 ; CHECK-LOB: tBcc %bb.10, 0 /* CC::eq */, killed $cpsr
195 ; CHECK-NOLOB: tB %bb.9, 14 /* CC::al */, $noreg
229 t2Bcc %bb.1, 13 /* CC::le */, killed $cpsr
236 t2Bcc %bb.9, 0 /* CC::eq */, killed $cpsr
260 t2Bcc %bb.7, 0 /* CC::eq */, killed $cpsr
261 t2B %bb.9, 14 /* CC::al */, $noreg
268 t2Bcc %bb.9, 0 /* CC::eq */, killed $cpsr
283 t2Bcc %bb.10, 0 /* CC::eq */, killed $cpsr
291 t2Bcc %bb.3, 1 /* CC::ne */, killed $cpsr
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dpeephole-mi.mir34 ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
35 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
79 ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
80 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
123 ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
124 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
163 ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
164 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
203 ; CHECK: tBcc %bb.2, 1 /* CC::ne */, $cpsr
204 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
[all …]
H A Dpeephole-cmp.mir28 ; CHECK: tBcc %bb.2, 8 /* CC::hi */, $cpsr
29 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
70 ; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
71 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
110 ; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
111 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
149 ; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
150 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
190 ; CHECK: tBcc %bb.2, 2 /* CC::hs */, $cpsr
191 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
[all …]

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