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Searched refs:CBZ (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dthumb2-bcc.ll2 ; If-conversion defeats the purpose of this test, which is to check CBZ
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcbz-implicit-it-range.ll4 ; Check that we do not produce a CBZ instruction to jump over the inline
H A Difcvt-size.mir310 # Here, the compare and conditional branch can be turned into a CBZ, so we
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX.td254 def : InstRW<[THXT8XWriteBR], (instregex "^CBZ")>;
H A DAArch64ISelLowering.h267 CBZ, enumerator
H A DAArch64SchedTSV110.td344 def : InstRW<[TSV110Wr_1cyc_1AB], (instregex "^(BR|RET|(CBZ|CBNZ|TBZ|TBNZ))$")>;
H A DAArch64SchedFalkorDetails.td1073 def : InstRW<[FalkorWr_1Z_0cyc], (instregex "^(BR|RET|(CBZ|CBNZ|TBZ|TBNZ)(W|X))$")>;
H A DAArch64SchedThunderX2T99.td407 (instregex "^CBZ", "^CBNZ", "^TBZ", "^TBNZ")>;
H A DAArch64SchedA64FX.td803 (instregex "^CBZ", "^CBNZ", "^TBZ", "^TBNZ")>;
H A DAArch64ISelLowering.cpp2203 MAKE_CASE(AArch64ISD::CBZ) in getTargetNodeName()
7655 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest); in LowerBR_CC()
18238 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest); in performBRCONDCombine()
H A DAArch64InstrInfo.td540 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
2499 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb-diagnostics.s310 @ CBZ/CBNZ - out of range immediates for branches
H A Dbasic-thumb2-instructions.s522 @ CBZ/CBNZ
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA57.td157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dthumb2.txt255 # CBZ/CBNZ