Home
last modified time | relevance | path

Searched refs:CAST (Results 1 – 25 of 64) sorted by relevance

123

/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dbuiltins-amdgcn-ci.cl39 // CHECK: [[CAST:%[0-9]+]] = bitcast i32* %{{[0-9]+}} to i8*
40 // CHECK: call i1 @llvm.amdgcn.is.shared(i8* [[CAST]]
46 // CHECK: [[CAST:%[0-9]+]] = bitcast i32* %{{[0-9]+}} to i8*
47 // CHECK: call i1 @llvm.amdgcn.is.private(i8* [[CAST]]
53 // CHECK: [[CAST:%[0-9]+]] = addrspacecast i32 addrspace(1)* %{{[0-9]+}} to i8*
54 // CHECK: call i1 @llvm.amdgcn.is.shared(i8* [[CAST]]
60 // CHECK: [[CAST:%[0-9]+]] = addrspacecast i32 addrspace(1)* %{{[0-9]+}} to i8*
61 // CHECK: call i1 @llvm.amdgcn.is.private(i8* [[CAST]]
H A Damdgcn-automatic-variable.cl64 // CHECK: %[[CAST:.+]] = bitcast [16 x [1 x float]] addrspace(5)* %a to i8 addrspace(5)*
65 // CHECK: call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 4 %[[CAST]], i8 0, i64 64, i1 fals…
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dscalable-cast-of-alloc.ll8 ; CHECK-NEXT: [[CAST:%.*]] = bitcast [16 x i32]* [[TMP]] to <vscale x 4 x i32>*
9 ; CHECK-NEXT: store volatile <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[CAST]], a…
27 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <vscale x 4 x i32>* [[TMP]] to <16 x i32>*
28 ; CHECK-NEXT: store <16 x i32> zeroinitializer, <16 x i32>* [[CAST]], align 64
29 ; CHECK-NEXT: [[RELOAD:%.*]] = load volatile <16 x i32>, <16 x i32>* [[CAST]], align 64
46 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <16 x i32>* [[TMP]] to <vscale x 4 x i32>*
65 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <vscale x 16 x i32>* [[TMP]] to <16 x i32>*
66 ; CHECK-NEXT: store volatile <16 x i32> zeroinitializer, <16 x i32>* [[CAST]], align 64
67 ; CHECK-NEXT: [[RELOAD:%.*]] = load volatile <16 x i32>, <16 x i32>* [[CAST]], align 64
84 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <vscale x 32 x i32>* [[TMP]] to <vscale x 16 x i32>*
[all …]
H A Dassoc-cast-assoc.ll6 ; CHECK-NEXT: [[CAST:%.*]] = zext i3 %a to i5
7 ; CHECK-NEXT: [[OP2:%.*]] = xor i5 [[CAST]], 15
18 ; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i1> %a to <2 x i32>
19 ; CHECK-NEXT: [[OP2:%.*]] = xor <2 x i32> [[CAST]], <i32 2, i32 1>
30 ; CHECK-NEXT: [[CAST:%.*]] = zext i3 %a to i5
31 ; CHECK-NEXT: [[OP2:%.*]] = or i5 [[CAST]], 11
42 ; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i2> %a to <2 x i32>
43 ; CHECK-NEXT: [[OP2:%.*]] = or <2 x i32> [[CAST]], <i32 3, i32 5>
H A Dbswap-inseltpoison.ll12 ; CHECK-NEXT: [[CAST:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]])
13 ; CHECK-NEXT: ret i32 [[CAST]]
24 ; CHECK-NEXT: [[CAST:%.*]] = call i32 @llvm.bswap.i32(i32 [[X1]])
25 ; CHECK-NEXT: ret i32 [[CAST]]
51 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[BSWAP]] to i32
52 ; CHECK-NEXT: ret i32 [[CAST]]
65 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <16 x i8> [[BSWAP]] to i128
66 ; CHECK-NEXT: ret i128 [[CAST]]
78 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[BSWAP]] to i32
79 ; CHECK-NEXT: ret i32 [[CAST]]
H A Dselect-cmp-cttz-ctlz.ll184 ; CHECK-NEXT: [[CAST:%.*]] = zext i16 [[CT]] to i32
185 ; CHECK-NEXT: ret i32 [[CAST]]
197 ; CHECK-NEXT: [[CAST:%.*]] = zext i16 [[CT]] to i64
198 ; CHECK-NEXT: ret i64 [[CAST]]
210 ; CHECK-NEXT: [[CAST:%.*]] = zext i32 [[CT]] to i64
211 ; CHECK-NEXT: ret i64 [[CAST]]
237 ; CHECK-NEXT: ret i32 [[CAST]]
250 ; CHECK-NEXT: ret i16 [[CAST]]
263 ; CHECK-NEXT: ret i16 [[CAST]]
276 ; CHECK-NEXT: ret i32 [[CAST]]
[all …]
H A Dicmp-bc-vec.ll78 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
79 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696648
93 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
94 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696647
H A Dicmp-bc-vec-inseltpoison.ll78 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
79 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696648
93 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
94 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696647
H A Dvscale_gep.ll27 ; CHECK-NEXT: [[CAST:%.*]] = bitcast i8* [[P:%.*]] to <vscale x 16 x i8>*
28 ; CHECK-NEXT: store <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8>* [[CAST]], align 16
29 ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* [[CAST]], i64…
/llvm-project-15.0.7/llvm/test/Transforms/JumpThreading/
H A Dindirectbr-cast-int-op.ll10 ; CHECK-NEXT: [[CAST:%.*]] = inttoptr i64 [[OP]] to i8*
11 ; CHECK-NEXT: indirectbr i8* [[CAST]], [label [[BB3:%.*]], label %bb2]
33 ; CHECK-NEXT: [[CAST:%.*]] = inttoptr i1 [[OP]] to i8*
34 ; CHECK-NEXT: indirectbr i8* [[CAST]], [label [[BB3:%.*]], label %bb2]
56 ; CHECK-NEXT: [[CAST:%.*]] = inttoptr i1 [[OP]] to i8*
57 ; CHECK-NEXT: indirectbr i8* [[CAST]], [label [[BB3:%.*]], label %bb2]
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dsink-addrspacecast.ll8 ; GEP: [[CAST:%[0-9]+]] = addrspacecast i64* %base to i8 addrspace(1)*
9 ; GEP: getelementptr inbounds i8, i8 addrspace(1)* [[CAST]], i64 40
25 ; GEP: [[CAST:%[0-9]+]] = addrspacecast i64* %base to i8 addrspace(1)*
26 ; GEP: getelementptr inbounds i8, i8 addrspace(1)* [[CAST]], i64 20
/llvm-project-15.0.7/llvm/test/Transforms/InferAddressSpaces/AMDGPU/
H A Dptrmask.ll8 ; CHECK-NEXT: [[CAST:%.*]] = addrspacecast i8 addrspace(3)* [[SRC_PTR:%.*]] to i8*
21 ; CHECK-NEXT: [[CAST:%.*]] = addrspacecast i8 addrspace(5)* [[SRC_PTR:%.*]] to i8*
34 ; CHECK-NEXT: [[CAST:%.*]] = addrspacecast i8 addrspace(2)* [[SRC_PTR:%.*]] to i8*
72 ; CHECK-NEXT: [[CAST:%.*]] = addrspacecast i8* [[MASKED]] to i8 addrspace(3)*
73 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8 addrspace(3)* [[CAST]], align 1
85 ; CHECK-NEXT: [[CAST:%.*]] = addrspacecast i8* [[MASKED]] to i8 addrspace(5)*
86 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8 addrspace(5)* [[CAST]], align 1
98 ; CHECK-NEXT: [[CAST:%.*]] = addrspacecast i8* [[MASKED]] to i8 addrspace(1)*
99 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8 addrspace(1)* [[CAST]], align 1
152 ; CHECK-NEXT: [[CAST:%.*]] = addrspacecast i8 addrspace(3)* [[SRC_PTR:%.*]] to i8*
[all …]
H A Dinfer-addrspacecast.ll20 ; CHECK: [[CAST:%.*]] = bitcast i32 addrspace(3)* [[GEP]] to i8 addrspace(3)*
21 ; CHECK-NEXT: store i8 8, i8 addrspace(3)* [[CAST]], align 8
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Daarch64-sve-explicit-casts-fixed-size.cpp25 #define CAST(from, to) \ macro
31 CAST(ty1, ty2) \
32 CAST(ty2, ty1)
/llvm-project-15.0.7/clang/test/Sema/
H A Daarch64-sve-explicit-casts-fixed-size.c24 #define CAST(from, to) \ macro
30 CAST(ty1, ty2) \
31 CAST(ty2, ty1)
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dvector-reverse.ll16 ; CHECK-NEXT: %[[CAST:.*]] = bitcast double* %[[GEP1]] to <8 x double>*
17 ; CHECK-NEXT: %[[WIDE:.*]] = load <8 x double>, <8 x double>* %[[CAST]], align 8
24 ; CHECK-NEXT: %[[CAST:.*]] = bitcast double* %[[GEP4]] to <8 x double>*
25 ; CHECK-NEXT: store <8 x double> %[[REVERSE6]], <8 x double>* %[[CAST]], align 8
51 ; CHECK-NEXT: %[[CAST:.*]] = bitcast i64* %[[GEP1]] to <8 x i64>*
52 ; CHECK-NEXT: %[[WIDE:.*]] = load <8 x i64>, <8 x i64>* %[[CAST]], align 8
/llvm-project-15.0.7/clang/test/CodeGenObjCXX/
H A Darc-cxx11-init-list.mm30 // CHECK-NEXT: [[CAST:%.*]] = bitcast [{{[0-9]+}} x %0*]* %{{.*}} to i8**
31 // CHECK-NEXT: store i8* [[INSTANCE]], i8** [[CAST]],
37 // CHECK-NEXT: [[CAST:%.*]] = bitcast [{{[0-9]+}} x %0*]* %{{.*}} to i8**
38 // CHECK-NEXT: store i8* [[INSTANCE]], i8** [[CAST]],
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/X86/
H A Dspeculate-cttz-ctlz.ll253 ; ALL-NEXT: [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
254 ; ALL-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 64, i32 [[CAST]]
299 ; ALL-NEXT: [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
300 ; ALL-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 64, i32 [[CAST]]
322 ; ALL-NEXT: [[CAST:%.*]] = trunc i64 [[TMP0]] to i16
323 ; ALL-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i16 64, i16 [[CAST]]
345 ; ALL-NEXT: [[CAST:%.*]] = trunc i32 [[TMP0]] to i16
346 ; ALL-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i16 32, i16 [[CAST]]
368 ; ALL-NEXT: [[CAST:%.*]] = trunc i64 [[TMP0]] to i16
369 ; ALL-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i16 64, i16 [[CAST]]
[all …]
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/llvm/
H A Dprefer-isa-or-dyn-cast-in-conditionals.cpp116 #define CAST(T, Obj) cast<T>(Obj) in foo() macro
122 if (auto x = CAST(X, y)) in foo()
/llvm-project-15.0.7/llvm/test/Transforms/Inline/
H A Dcgscc-cycle.ll49 ; CHECK: %[[CAST:.*]] = bitcast i8** %[[A]] to void (i8*, i1, i32)**
50 ; CHECK: %[[P:.*]] = load void (i8*, i1, i32)*, void (i8*, i1, i32)** %[[CAST]]
92 ; CHECK: %[[CAST:.*]] = bitcast i8** %[[A]] to void (i8*, i8*, i1, i32)**
93 ; CHECK: %[[P:.*]] = load void (i8*, i8*, i1, i32)*, void (i8*, i8*, i1, i32)** %[[CAST]]
120 ; CHECK: %[[CAST:.*]] = bitcast i8** %[[A]] to void (i8*, i8*, i1, i32)**
121 ; CHECK: %[[P:.*]] = load void (i8*, i8*, i1, i32)*, void (i8*, i8*, i1, i32)** %[[CAST]]
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/google/
H A Dreadability-casting.cpp191 #define CAST(type, value) (type)(value) macro
193 int i = CAST(int, d); in macros()
/llvm-project-15.0.7/llvm/test/Instrumentation/HWAddressSanitizer/
H A Dexception-lifetime.ll24 ; CHECK: [[CAST:%.*]] = bitcast { i32, [12 x i8] }* %x to i32*
25 ; CHECK: [[TMP1:%.*]] = bitcast i32* {{.*}}[[CAST]] to i8*
/llvm-project-15.0.7/llvm/test/Transforms/TypePromotion/ARM/
H A Dlarge-int.ll7 ; CHECK-NEXT: [[CAST:%.*]] = bitcast i8* [[IN:%.*]] to i144*
8 ; CHECK-NEXT: [[LOAD:%.*]] = load i144, i144* [[CAST]], align 4
/llvm-project-15.0.7/llvm/test/Transforms/RewriteStatepointsForGC/
H A Dscalar-base-vector.ll19 ; CHECK-NEXT: [[CAST:%.*]] = bitcast i8 addrspace(1)* [[PHI]] to i32 addrspace(1)*
20 …nsertelement <2 x i32 addrspace(1)*> zeroinitializer, i32 addrspace(1)* [[CAST]], i32 0, !is_base_…
54 ; CHECK-NEXT: [[CAST:%.*]] = bitcast i8 addrspace(1)* [[BASE]] to i32 addrspace(1)*
55 …nsertelement <2 x i32 addrspace(1)*> zeroinitializer, i32 addrspace(1)* [[CAST]], i32 0, !is_base_…
102 ; CHECK-NEXT: [[CAST:%.*]] = bitcast i8 addrspace(1)* [[BASE]] to i32 addrspace(1)*
103 …nsertelement <2 x i32 addrspace(1)*> zeroinitializer, i32 addrspace(1)* [[CAST]], i32 0, !is_base_…
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-interleaved-ld-combine.ll15 ; CHECK-DAG: [[CAST:%.+]] = bitcast <4 x float>* [[GEP]] to <16 x float>*
16 ; CHECK-DAG: [[LOAD:%.+]] = load <16 x float>, <16 x float>* [[CAST]], align 16
61 ; CHECK-DAG: [[CAST:%.+]] = bitcast <4 x float>* [[GEP]] to <16 x float>*
62 ; CHECK-DAG: [[LOAD:%.+]] = load <16 x float>, <16 x float>* [[CAST]], align 16
123 ; CHECK-DAG: [[CAST:%.+]] = bitcast <4 x float>* [[GEP]] to <16 x float>*
124 ; CHECK-DAG: [[LOAD:%.+]] = load <16 x float>, <16 x float>* [[CAST]], align 4
181 ; CHECK-DAG: [[CAST:%.+]] = bitcast <4 x float>* [[GEP]] to <8 x float>*
182 ; CHECK-DAG: [[LOAD:%.+]] = load <8 x float>, <8 x float>* [[CAST]], align 16
213 ; CHECK-DAG: [[CAST:%.+]] = bitcast <4 x float>* [[GEP]] to <12 x float>*
214 ; CHECK-DAG: [[LOAD:%.+]] = load <12 x float>, <12 x float>* [[CAST]], align 16

123