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Searched refs:CAS (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Datomics-cas-remarks-gfx90a.ll15 ; GFX90A-CAS-LABEL: atomic_add_cas:
17 ; GFX90A-CAS: s_cbranch_execnz
26 ; GFX90A-CAS: s_cbranch_execnz
35 ; GFX90A-CAS: s_cbranch_execnz
44 ; GFX90A-CAS: s_cbranch_execnz
53 ; GFX90A-CAS: s_cbranch_execnz
62 ; GFX90A-CAS: s_cbranch_execnz
71 ; GFX90A-CAS: s_cbranch_execnz
80 ; GFX90A-CAS: s_cbranch_execnz
89 ; GFX90A-CAS: s_cbranch_execnz
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Darm64-atomic-128.ll32 ; CHECK-CAS-O1: // %bb.0:
41 ; CHECK-CAS-O1-NEXT: ret
85 ; CHECK-CAS-O0-NEXT: ret
126 ; CHECK-CAS-O1-NEXT: ret
170 ; CHECK-CAS-O0-NEXT: ret
211 ; CHECK-CAS-O1-NEXT: ret
255 ; CHECK-CAS-O0-NEXT: ret
296 ; CHECK-CAS-O1-NEXT: ret
340 ; CHECK-CAS-O0-NEXT: ret
372 ; CHECK-CAS-O1-NEXT: ret
[all …]
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Datomics-cas-remarks-gfx90a.cl7 // RUN: FileCheck %s --check-prefix=GFX90A-CAS
33 // GFX90A-CAS-LABEL: @atomic_cas
34 // GFX90A-CAS: atomicrmw fadd float addrspace(1)* {{.*}} syncscope("workgroup-one-as") monotonic
35 // GFX90A-CAS: atomicrmw fadd float addrspace(1)* {{.*}} syncscope("agent-one-as") monotonic
36 // GFX90A-CAS: atomicrmw fadd float addrspace(1)* {{.*}} syncscope("one-as") monotonic
37 // GFX90A-CAS: atomicrmw fadd float addrspace(1)* {{.*}} syncscope("wavefront-one-as") monotonic
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/
H A Dtsan_interface_atomic.cpp738 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic8_compare_exchange_strong()
744 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic16_compare_exchange_strong()
750 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic32_compare_exchange_strong()
756 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic64_compare_exchange_strong()
763 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic128_compare_exchange_strong()
770 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic8_compare_exchange_weak()
776 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic16_compare_exchange_weak()
782 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic32_compare_exchange_weak()
788 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic64_compare_exchange_weak()
795 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic128_compare_exchange_weak()
[all …]
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl/
H A Dtsan_interface_atomic.cpp743 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic8_compare_exchange_strong()
749 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic16_compare_exchange_strong()
755 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic32_compare_exchange_strong()
761 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic64_compare_exchange_strong()
768 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic128_compare_exchange_strong()
775 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic8_compare_exchange_weak()
781 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic16_compare_exchange_weak()
787 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic32_compare_exchange_weak()
793 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic64_compare_exchange_weak()
800 ATOMIC_IMPL(CAS, a, c, v, mo, fmo); in __tsan_atomic128_compare_exchange_weak()
[all …]
/llvm-project-15.0.7/compiler-rt/lib/builtins/aarch64/
H A Dlse.S124 #define CAS GLUE4(cas, A, L, S) s(0), s(1), [x2] macro
126 #define CAS .inst 0x08a07c41 + B + M macro
128 CAS // s(0), s(1), [x2]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1302 MachineInstrBuilder CAS; in legalizeAtomicCmpxchg128() local
1346 CAS = MIRBuilder.buildInstr(Opcode, {CASDst}, {CASDesired, CASNew, Addr}); in legalizeAtomicCmpxchg128()
1373 CAS = MIRBuilder.buildInstr(Opcode, {DstLo, DstHi, Scratch}, in legalizeAtomicCmpxchg128()
1379 CAS.cloneMemRefs(MI); in legalizeAtomicCmpxchg128()
1380 constrainSelectedInstRegOperands(*CAS, *ST->getInstrInfo(), in legalizeAtomicCmpxchg128()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td85 def WriteAtomic : SchedWrite; // Atomic memory operations (CAS, Swap, LDOP)
H A DAArch64SchedExynosM5.td691 def : InstRW<[M5WriteLGW], (instregex "^CAS(A|AL|L)?[BHW]$")>;
692 def : InstRW<[M5WriteLGX], (instregex "^CAS(A|AL|L)?X$")>;
H A DAArch64InstrAtomics.td539 defm : CASregister_patterns<"CAS", "atomic_cmp_swap">;
H A DAArch64InstrFormats.td11152 // * CAS
11160 // CAS SZ |001000|1 |A |1 |Rs |R |11111 |Rn |Rt
11168 // CAS{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
11169 // CAS{<order>} <Xs>, <Xt>, [<Xn|SP>]
H A DAArch64InstrInfo.td1891 // v8.1 atomic CAS
1892 defm CAS : CompareAndSwap<0, 0, "">;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp622 } else if (AtomicCmpXchgInst *CAS = dyn_cast<AtomicCmpXchgInst>(UseInst)) { in collectUsesWithPtrTypes() local
623 if (CAS->isVolatile()) in collectUsesWithPtrTypes()
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Datomic-acquire-comment.s172 ; CAS instructions aren't affected.
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Datomics-with-scope.ll133 ; CAS is implemented separately and has more arguments
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td418 // CAS is preferred for sparc v9.
1636 // The CAS instruction, unlike other instructions, only comes in a
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.td787 // Multiclass for CAS instructions.
1140 // Section 8.2.20 - CAS (Compare and Swap)
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Datomic-mi.ll103 ; These are implemented with a CAS loop on 32 bit architectures, and thus