| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/ |
| H A D | legalize-inserts.mir | 183 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
184 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
187 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C7]]
189 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C7]]
192 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C7]]
195 ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C7]]
198 ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C7]]
201 ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C7]]
204 ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C7]]
208 ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C7]]
[all …]
|
| H A D | call-lowering-sret-demotion.ll | 31 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
32 ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C7]](s64)
71 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
72 ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C7]](s64)
111 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
112 ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C7]](s64)
|
| H A D | arm64-callingconv-ios.ll | 18 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
40 ; CHECK-NEXT: G_STORE [[C7]](s64), [[PTR_ADD4]](p0) :: (store (s64) into stack + 32, align 1)
63 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
91 ; CHECK-NEXT: $x7 = COPY [[C7]](s64)
|
| H A D | inline-memcpy-forced.mir | 74 ; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 127
75 ; CHECK: [[PTR_ADD14:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C7]](s64)
77 ; CHECK: [[PTR_ADD15:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C7]](s64)
|
| H A D | irtranslator-switch-bittest.ll | 38 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
39 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]]
108 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
109 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C7]], [[ZEXT]](s64)
303 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
304 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]]
365 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
366 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]]
|
| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | dcl_ambig_res.cpp | 58 class C7 { }; class
59 void f7(int(C7)) { } // expected-note{{candidate}} in f7() argument
60 int g7(C7);
66 void h7(int *(C7[10])) { } // expected-note{{previous}} in h7()
67 void h7(int *(*_fp)(C7 _parm[10])) { } // expected-error{{redefinition}} in h7()
|
| H A D | friend2.cpp | 68 template<typename T> struct C7 { struct
72 C7<long> c7a;
73 C7<int*> c7b; // expected-note{{in instantiation of template class 'C7<int *>' requested here}}
|
| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | lto-visibility-inference.cpp | 31 struct C7 { struct
68 void f(C1 *c1, C2 *c2, C3 *c3, C4 *c4, C5 *c5, C6 *c6, std::C7 *c7, in f()
69 std::C7::C8 *c8, stdext::C9 *c9, other::C10 *c10) { in f()
|
| H A D | vtable-layout-extreme.cpp | 56 class C7 class
67 : public C7
|
| H A D | debug-info-use-after-free.cpp | 286 C7 { class
299 n1::C7 <
|
| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | pr38539.ll | 51 %C7 = icmp uge i1 false, %C15
52 store i1 %C7, ptr undef
55 %B30 = srem i1 %C19, %C7
106 %C7 = icmp uge i1 false, %C15
107 store i1 %C7, ptr undef
110 %B30 = srem i1 %C19, %C7
|
| /llvm-project-15.0.7/libcxxabi/test/ |
| H A D | dynamic_cast.pass.cpp | 40 struct C7 : virtual C3 { Pad4 _; }; argument
41 struct C9 : C6, C7 { Pad5 _; };
51 assert(dynamic_cast<C7*>(c3) == static_cast<C7*>(&c9)); in test()
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ |
| H A D | ctpop.mir | 32 ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
33 ; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
72 ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
73 ; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
85 ; MIPS32: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C7]](s32)
|
| H A D | bitreverse.mir | 47 ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
50 ; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32)
51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
127 ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
130 ; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32)
131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
154 ; MIPS32: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[C7]](s32)
155 ; MIPS32: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[OR10]], [[C7]](s32)
|
| /llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/infrastructure/ |
| H A D | nolintbeginend.cpp | 63 class C7 { C7(int i); }; class
|
| H A D | nolint.cpp | 34 class C7 { C7(int i); }; // NOLINTNEXTLINE class
|
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | aix-tls-gd-int.ll | 239 ; SMALL32-NEXT: lwz 4, L..C7(2)
256 ; LARGE32-NEXT: lwz 4, L..C7@l(4)
271 ; SMALL64-NEXT: ld 4, L..C7(2)
288 ; LARGE64-NEXT: ld 4, L..C7@l(4)
554 ; SMALL32-NEXT: lwz 4, L..C7(2)
591 ; SMALL64-NEXT: ld 4, L..C7(2)
610 ; LARGE64-NEXT: ld 4, L..C7@l(4)
652 ; SMALL32-LABEL: L..C7:
672 ; LARGE32-LABEL: L..C7:
692 ; SMALL64-LABEL: L..C7:
[all …]
|
| H A D | aix-tls-gd-double.ll | 226 ; SMALL32-NEXT: lwz 4, L..C7(2)
242 ; LARGE32-NEXT: lwz 4, L..C7@l(4)
256 ; SMALL64-NEXT: ld 4, L..C7(2)
272 ; LARGE64-NEXT: ld 4, L..C7@l(4)
538 ; SMALL32-NEXT: lwz 4, L..C7(2)
575 ; SMALL64-NEXT: ld 4, L..C7(2)
594 ; LARGE64-NEXT: ld 4, L..C7@l(4)
636 ; SMALL32-LABEL: L..C7:
656 ; LARGE32-LABEL: L..C7:
676 ; SMALL64-LABEL: L..C7:
[all …]
|
| H A D | aix-tls-gd-longlong.ll | 252 ; SMALL32-NEXT: lwz 4, L..C7(2)
271 ; LARGE32-NEXT: lwz 4, L..C7@l(4)
287 ; SMALL64-NEXT: ld 4, L..C7(2)
304 ; LARGE64-NEXT: ld 4, L..C7@l(4)
588 ; SMALL32-NEXT: lwz 4, L..C7(2)
631 ; SMALL64-NEXT: ld 4, L..C7(2)
650 ; LARGE64-NEXT: ld 4, L..C7@l(4)
692 ; SMALL32-LABEL: L..C7:
712 ; LARGE32-LABEL: L..C7:
732 ; SMALL64-LABEL: L..C7:
[all …]
|
| /llvm-project-15.0.7/clang/test/CXX/expr/expr.prim/expr.prim.id/ |
| H A D | p3.cpp | 135 concept C7 = sizeof(T) == 1 || sizeof(
144 static_assert(C7<char>);
145 static_assert(!C7<short>); // expected-note{{while checking the satisfaction of concept 'C7<short>'…
|
| /llvm-project-15.0.7/clang/test/Parser/ |
| H A D | cxx2a-concept-declaration.cpp | 52 template<typename T> concept bool C7 = true;
58 template<> concept C7<int> = false;
|
| /llvm-project-15.0.7/libc/AOR_v20.02/math/ |
| H A D | v_sin.c | 25 #define C7 v_f64 (Poly[0]) macro
71 y = v_fma_f64 (C7, r2, C6); in V_NAME()
|
| H A D | v_cos.c | 25 #define C7 v_f64 (Poly[0]) macro
72 y = v_fma_f64 (C7, r2, C6); in V_NAME()
|
| /llvm-project-15.0.7/mlir/test/Transforms/ |
| H A D | single-parallel-loop-collapsing.mlir | 20 // CHECK-DAG: [[C7:%.*]] = arith.constant 7 : index
28 // CHECK: [[I1:%.*]] = arith.addi [[V0]], [[C7]] : index
|
| /llvm-project-15.0.7/llvm/test/FileCheck/dump-input/ |
| H A D | context.txt | 99 ; C7-NEXT: 31: foo7
100 ; C7-NEXT: 32: foo8
101 ; C7-NEXT: 33: foo9
102 ; C7-NEXT: 34: foo0
215 ; RUN: | FileCheck %s -match-full-lines -check-prefixes=C0,C1,C2,C3,C4,C5,C6,C7
221 ; RUN: | FileCheck %s -match-full-lines -check-prefixes=C0,C1,C2,C3,C4,C5,C6,C7
|