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/llvm-project-15.0.7/mlir/test/Conversion/TosaToArith/
H A Dtosa-to-arith.mlir23 // CHECK-DAG: %[[C32:.+]] = arith.constant 32 : i32
35 // CHECK-DAG: %[[OVER31:.+]] = arith.cmpi sge, %[[S32]], %[[C32]]
36 // CHECK-DAG: %[[OVER32:.+]] = arith.cmpi sgt, %[[S32]], %[[C32]]
37 // CHECK-DAG: %[[HISHLN:.+]] = arith.subi %[[C32]], %[[S32]]
38 // CHECK-DAG: %[[HISHRN:.+]] = arith.subi %[[S32]], %[[C32]]
/llvm-project-15.0.7/mlir/test/Dialect/Math/
H A Dexpand-math.mlir30 // CHECK: %[[C32:.+]] = arith.constant 32 : i32
32 …// CHECK: %[[WHILE:.+]]:3 = scf.while (%[[A1:.+]] = %arg0, %[[A2:.+]] = %[[C32]], %[[A3:.+]] = %[[…
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dshifts.cl25 //OPT-NEXT: [[C32:%.+]] = shl i32 %a, [[M32]]
28 //OPT-NEXT: [[E32:%.+]] = add nsw i32 [[C32]], 2
/llvm-project-15.0.7/llvm/test/tools/llvm-nm/Inputs/
H A Dbitcode-sym32.ll3 @C32 = dso_local global i32 5, align 4
/llvm-project-15.0.7/llvm/test/tools/llvm-ar/Inputs/
H A Dbitcode-sym32.ll3 @C32 = dso_local global i32 5, align 4
/llvm-project-15.0.7/llvm/test/tools/llvm-nm/
H A Dbitcode-export-sym.test9 # CHECK: C32
H A Doption-X.test19 # BITCODE32-NEXT: C32
/llvm-project-15.0.7/lldb/test/Shell/SymbolFile/NativePDB/
H A Dtag-types.cpp21 char32_t C32; member
/llvm-project-15.0.7/mlir/include/mlir/ExecutionEngine/
H A DSparseTensorUtils.h102 DO(C32, complex32)
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16-instructions.ll736 ; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]]
737 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], [[C32]];
754 ; XCHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]]
755 ; XCHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], [[C32]];
949 ; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]]
950 ; CHECK-NOF16-NEXT: fma.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]], [[C32]];
1150 ; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]]
1151 ; CHECK-NOF16-NEXT: fma.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]], [[C32]];
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dtile-and-fuse-tensors.mlir272 // CHECK-DAG: %[[C32:.*]] = arith.constant 32 : index
277 // CHECK: scf.for %{{.*}} = %[[C0]] to %[[C128]] step %[[C32]]
/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/
H A Dfunnel_shift.ll68 ; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 [[C32:%.*]…
70 ; CHECK-NEXT: [[I32:%.*]] = call i32 @llvm.fshl.i32(i32 [[A32:%.*]], i32 [[B32:%.*]], i32 [[C32]…
236 ; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 [[C32:%.*]…
238 ; CHECK-NEXT: [[I32:%.*]] = call i32 @llvm.fshl.i32(i32 [[A32:%.*]], i32 [[A32]], i32 [[C32]])
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-implicit-def-s1025.mir368 ; FIJI-NEXT: [[C32:%[0-9]+]]:_(s32) = G_CONSTANT i32 18
369 ; FIJI-NEXT: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C32]](s32)
H A Dlegalize-ctpop.mir713 ; CHECK-NEXT: [[C32:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
714 ; CHECK-NEXT: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[AND79]], [[C32]](s32)
H A Dlegalize-insert-vector-elt.mir542 ; CHECK-NEXT: [[C32:%[0-9]+]]:_(s32) = G_CONSTANT i32 116
543 ; CHECK-NEXT: [[PTR_ADD31:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C32]](s32)
H A Dlegalize-extract-vector-elt.mir1537 ; CHECK-NEXT: [[C32:%[0-9]+]]:_(s32) = G_CONSTANT i32 120
1538 ; CHECK-NEXT: [[PTR_ADD32:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C32]](s32)
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dcanonicalize.mlir801 // CHECK-NEXT: %[[C32:.*]] = arith.constant 32 : i32
810 // CHECK: return %[[FOR_RES]], %[[C32]] : i32, i32
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Darm64-irtranslator-switch.ll264 ; CHECK: [[C32:%[0-9]+]]:_(s32) = G_CONSTANT i32 36
505 ; CHECK: [[ICMP32:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C32]]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp2253 const ConstantInt *C32 = ConstantInt::get(Ty, static_cast<int64_t>(V32)); in evaluate() local
2254 Result.add(C32); in evaluate()
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Darith-add-saddo.ll771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A32]], i8 [[B32]])
835 ; CHECK-NEXT: [[R32:%.*]] = extractvalue { i8, i1 } [[C32]], 0
H A Darith-add-uaddo.ll771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[A32]], i8 [[B32]])
835 ; CHECK-NEXT: [[R32:%.*]] = extractvalue { i8, i1 } [[C32]], 0
H A Darith-mul-umulo.ll771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[A32]], i8 [[B32]])
835 ; CHECK-NEXT: [[R32:%.*]] = extractvalue { i8, i1 } [[C32]], 0
H A Darith-mul-smulo.ll771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[A32]], i8 [[B32]])
835 ; CHECK-NEXT: [[R32:%.*]] = extractvalue { i8, i1 } [[C32]], 0
H A Darith-sub-ssubo.ll771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 [[A32]], i8 [[B32]])
835 ; CHECK-NEXT: [[R32:%.*]] = extractvalue { i8, i1 } [[C32]], 0
H A Darith-sub-usubo.ll771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[A32]], i8 [[B32]])
835 ; CHECK-NEXT: [[R32:%.*]] = extractvalue { i8, i1 } [[C32]], 0

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