Home
last modified time | relevance | path

Searched refs:C23 (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/infrastructure/
H A Dnolint.cpp79 class C23 { C23(int i); }; // NOLINT (some-other-check) class
/llvm-project-15.0.7/clang/test/Parser/
H A Dcxx2a-concept-declaration.cpp97 template <bool word> concept C23 = integral_constant<bool, wor>::value;
/llvm-project-15.0.7/clang/test/Misc/
H A Ddiag-template-diffing.cpp590 template <class T> using C23 = D23<T>; typedef
591 typedef const C23<int> B23;
597 foo23(C23<char>()); in test23()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td238 def C23 : Ri< 23, "C23">;
315 def C22_C23 : Rdi<22, "C22", [C22, C23]>;
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-implicit-def-s1025.mir194 ; TAHITI-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
195 ; TAHITI-NEXT: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C23]](s32)
320 ; FIJI-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
321 ; FIJI-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C23]](s32)
H A Dlegalize-merge-values.mir757 ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
758 ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[COPY23]], [[C23]](s32)
860 ; CHECK-NEXT: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[COPY55]], [[C23]](s32)
954 ; CHECK-NEXT: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY87]], [[C23]](s32)
H A Dlegalize-extract-vector-elt.mir1510 ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 84
1511 ; CHECK-NEXT: [[PTR_ADD23:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C23]](s32)
1710 ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
1711 ; CHECK-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C23]](s32)
1797 ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C23]](s32)
H A Dlegalize-ctpop.mir668 ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
669 ; CHECK-NEXT: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[AND70]], [[C23]](s32)
H A Dlegalize-insert-vector-elt.mir506 ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 80
507 ; CHECK-NEXT: [[PTR_ADD22:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C23]](s32)
H A Dirtranslator-call.ll5090 ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
5091 ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C23]](s32)
5233 ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
5234 ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C23]](s32)
H A Dlegalize-load-global.mir16487 ; SI-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
16488 ; SI-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C23]](s32)
16557 ; CI-HSA-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
16558 ; CI-HSA-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C23]](s32)
16627 ; CI-MESA-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
16628 ; CI-MESA-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C23]](s32)
16697 ; VI-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
16698 ; VI-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C23]](s32)
16767 ; GFX9-HSA-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
16768 ; GFX9-HSA-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C23]](s32)
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp132 SP::C20, SP::C21, SP::C22, SP::C23,
/llvm-project-15.0.7/libclc/generic/lib/math/
H A Dsincos_helpers.cl290 // pi/2 = C90 FDA A22 168 C23 4C4
/llvm-project-15.0.7/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp201 Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Darm64-irtranslator-switch.ll255 ; CHECK: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
460 ; CHECK: [[ICMP23:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C23]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dinduction.ll5747 ; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[C23:%.*]], [[LOOP]] ], [ [[TMP12]], [[MIDDLE_BLOCK]…
5750 ; CHECK-NEXT: [[C5:%.*]] = phi i64 [ [[C23]], [[LOOP]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
5765 ; CHECK-NEXT: [[C23]] = add i64 [[C13]], [[C16]]
5811 ; IND-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[C23:%.*]], [[LOOP]] ], [ [[TMP12]], [[MIDDLE_BLOCK]] ]
5814 ; IND-NEXT: [[C5:%.*]] = phi i64 [ [[C23]], [[LOOP]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
5829 ; IND-NEXT: [[C23]] = add i64 [[C13]], [[C16]]
5894 ; UNROLL-NEXT: [[C5:%.*]] = phi i64 [ [[C23]], [[LOOP]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
5909 ; UNROLL-NEXT: [[C23]] = add i64 [[C13]], [[C16]]
5991 ; UNROLL-NO-IC-NEXT: [[C23]] = add i64 [[C13]], [[C16]]
6056 ; INTERLEAVE-NEXT: [[C5:%.*]] = phi i64 [ [[C23]], [[LOOP]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]]…
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Darith-add-saddo.ll371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 [[A23]], i16 [[B23…
403 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i16, i1 } [[C23]], 0
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A23]], i8 [[B23]])
826 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i8, i1 } [[C23]], 0
H A Darith-add-uaddo.ll371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 [[A23]], i16 [[B23…
403 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i16, i1 } [[C23]], 0
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[A23]], i8 [[B23]])
826 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i8, i1 } [[C23]], 0
H A Darith-mul-umulo.ll371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 [[A23]], i16 [[B23…
403 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i16, i1 } [[C23]], 0
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[A23]], i8 [[B23]])
826 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i8, i1 } [[C23]], 0
H A Darith-mul-smulo.ll371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 [[A23]], i16 [[B23…
403 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i16, i1 } [[C23]], 0
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[A23]], i8 [[B23]])
826 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i8, i1 } [[C23]], 0
H A Darith-sub-ssubo.ll371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 [[A23]], i16 [[B23…
403 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i16, i1 } [[C23]], 0
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 [[A23]], i8 [[B23]])
826 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i8, i1 } [[C23]], 0
H A Darith-sub-usubo.ll371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 [[A23]], i16 [[B23…
403 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i16, i1 } [[C23]], 0
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[A23]], i8 [[B23]])
826 ; CHECK-NEXT: [[R23:%.*]] = extractvalue { i8, i1 } [[C23]], 0
/llvm-project-15.0.7/clang/docs/
H A DLanguageExtensions.rst4628 Clang supports the C23 ``_BitInt(N)`` feature as an extension in older C modes
/llvm-project-15.0.7/clang-tools-extra/clang-tidy/misc/ConfusableTable/
H A Dconfusables.txt5790 0CA3 ; 0C23 ; MA # ( ಣ → ణ ) KANNADA LETTER NNA → TELUGU LETTER NNA #
7612 2E8F ; 5C23 ; MA #* ( ⺏ → 尣 ) CJK RADICAL LAME TWO → CJK UNIFIED IDEOGRAPH-5C23 #