Home
last modified time | relevance | path

Searched refs:C12 (Results 1 – 25 of 45) sorted by relevance

12

/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/infrastructure/
H A Dnolintbeginend.cpp115 class C12 { C12(int i); }; class
H A Dnolint.cpp52 class C12 { C12(int i); }; // NOLINT(some-other-check) NOLINT(google-explicit-constructor) class
/llvm-project-15.0.7/mlir/test/Transforms/
H A Dparallel-loop-collapsing.mlir31 // CHECK-DAG: [[C12:%.*]] = arith.constant 12 : index
45 // CHECK: "magic.op"([[I0]], [[C3]], [[C6]], [[I3]], [[C12]]) : (index, index, index, index, inde…
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Darm64-callingconv-ios.ll38 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
39 ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
70 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
71 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
H A Dcombine-udiv.mir84 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 5
97 …; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C10]](s16), [[C12]](s16), …
152 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 -5617
162 …; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C9]](s16), [[C12]](s16), […
214 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 18351
222 …CTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C8]](s16), [[C10]](s16), [[C12]](s16), [[C13]](s16…
316 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 -8079
325 …ECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C8]](s16), [[C9]](s16), [[C12]](s16), [[C13]](s16…
H A Dcall-translator-ios.ll27 ; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 12
34 ; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store (s8) into stack + 1)
H A Dcall-translator.ll231 ; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
240 ; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store (s64) into stack + 8, align 1)
H A Darm64-callingconv.ll199 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
200 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
H A Dcombine-unmerge.mir208 ; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 4
224 ; CHECK: $b12 = COPY [[C12]](s8)
H A Darm64-irtranslator-switch.ll244 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
405 ; CHECK: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C12]]
1098 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 283
1183 ; CHECK: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C12]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-fptrunc.mir130 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
131 ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
211 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
212 ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
262 ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[C12]]
338 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
339 ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
419 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
420 ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
470 ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[C12]]
H A Dregbankselect-extract-vector-elt.mir88 ; WAVE64-NEXT: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 13
141 ; WAVE32-NEXT: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 13
238 ; WAVE64-NEXT: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 13
291 ; WAVE32-NEXT: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 13
611 ; WAVE64-NEXT: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
667 ; WAVE32-NEXT: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
740 ; WAVE64-NEXT: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
796 ; WAVE32-NEXT: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
869 ; WAVE64-NEXT: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
925 ; WAVE32-NEXT: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
[all …]
H A Dlegalize-ctpop.mir308 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
309 ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C12]](s16)
331 ; CHECK-NEXT: [[LSHR24:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C12]](s16)
346 ; CHECK-NEXT: [[LSHR39:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C12]](s16)
361 ; CHECK-NEXT: [[LSHR54:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C12]](s16)
392 ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s16) = G_SHL [[AND10]], [[C12]](s16)
438 ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(s16) = G_SHL [[AND26]], [[C12]](s16)
484 ; CHECK-NEXT: [[SHL37:%[0-9]+]]:_(s16) = G_SHL [[AND42]], [[C12]](s16)
530 ; CHECK-NEXT: [[SHL52:%[0-9]+]]:_(s16) = G_SHL [[AND58]], [[C12]](s16)
577 ; CHECK-NEXT: [[SHL67:%[0-9]+]]:_(s16) = G_SHL [[COPY9]], [[C12]](s16)
[all …]
H A Dlegalize-implicit-def-s1025.mir55 ; TAHITI-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
56 ; TAHITI-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
105 ; TAHITI-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
152 ; TAHITI-NEXT: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND41]], [[C12]](s32)
259 ; FIJI-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 12
260 ; FIJI-NEXT: [[LSHR12:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C12]](s16)
278 ; FIJI-NEXT: [[LSHR27:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C12]](s16)
H A Dlegalize-merge-values.mir350 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
351 ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C12]](s32)
400 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
401 ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C12]](s32)
516 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
517 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C12]], [[C7]]
713 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
714 ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C12]](s32)
827 ; CHECK-NEXT: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[COPY44]], [[C12]](s32)
921 ; CHECK-NEXT: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY76]], [[C12]](s32)
H A Dlegalize-insert-vector-elt.mir257 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 208
258 ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C12]](s64)
295 ; CHECK-NEXT: [[PTR_ADD27:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY1]], [[C12]](s64)
378 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 176
379 ; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY1]], [[C12]](s64)
462 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 36
463 ; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C12]](s32)
/llvm-project-15.0.7/clang/test/Parser/
H A Dcxx2a-concept-declaration.cpp74 template<bool x> concept C12 = 2 && x; // expected-error {{atomic constraint must be of type 'bool'…
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td227 def C12 : Ri< 12, "C12">;
310 def C12_C13 : Rdi<12, "C12", [C12, C13]>;
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dfriend2.cpp100 template<typename T> class C12 { class
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dresolve-shaped-type-result-dims.mlir273 // CHECK-DAG: %[[C12:.+]] = arith.constant 12 : index
278 // CHECK: return %[[C12]], %[[OUT_DIM1]], %[[OUT_DIM2]]
H A Dtile.mlir148 // TILE-234-DAG: %[[C12:.*]] = arith.constant 12 : index
150 // TILE-234: scf.for %[[J:.*]] = %{{.*}}{{.*}} to %[[C12]] step %{{.*}} {
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.cpp128 SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15
/llvm-project-15.0.7/llvm/test/CodeGen/M68k/GlobalISel/
H A Dirtranslator-call.ll198 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
199 ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY5]], [[C12]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dextract_vector_dynelt.ll384 ; GCN-DAG: s_cselect_b64 [[C12:[^,]+]], -1, 0
402 ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V12:v[0-9]+]], {{[^,]+}}, [[V11]], [[C12]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dif-reduction.ll613 ; CHECK-DAG: %[[C12:.*]] = select <4 x i1> %[[C11]], <4 x i1> %[[C2]], <4 x i1> zeroinitializer
681 ; CHECK-DAG: %[[C12:.*]] = select <4 x i1> %[[C11]], <4 x i1> %[[C2]], <4 x i1> zeroinitializer
684 ; CHECK: %[[S1:.*]] = select <4 x i1> %[[C12]], <4 x float> %[[SUB]], <4 x float> %[[ADD]]

12