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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dartifact-combiner-cse-leaves-dead-cast.mir53 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
55 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT]], [[C10]]
57 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT1]], [[C10]]
61 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SEXT2]], [[C10]]
65 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SEXT3]], [[C10]]
69 ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SEXT4]], [[C10]]
71 ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SEXT5]], [[C10]]
75 ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SEXT6]], [[C10]]
79 ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SEXT7]], [[C10]]
H A Dlegalize-fptrunc.mir125 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
126 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD]]
137 ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD]](s32), [[C10]]
206 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
207 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD]]
259 ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD2]]
333 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
334 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD]]
414 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
415 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD]]
[all …]
H A Dlegalize-merge-values.mir261 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
262 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
279 ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C10]](s32)
321 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
322 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
392 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
460 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
502 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
503 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[C10]], [[C7]]
640 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
[all …]
H A Dregbankselect-extract-vector-elt.mir82 ; WAVE64-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 11
135 ; WAVE32-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 11
232 ; WAVE64-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 11
285 ; WAVE32-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 11
605 ; WAVE64-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
661 ; WAVE32-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
734 ; WAVE64-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
790 ; WAVE32-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
863 ; WAVE64-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
919 ; WAVE32-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
[all …]
H A Dlegalize-ctpop.mir304 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
305 ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C10]](s16)
329 ; CHECK-NEXT: [[LSHR22:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C10]](s16)
344 ; CHECK-NEXT: [[LSHR37:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C10]](s16)
359 ; CHECK-NEXT: [[LSHR52:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C10]](s16)
386 ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[AND8]], [[C10]](s16)
432 ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(s16) = G_SHL [[AND24]], [[C10]](s16)
478 ; CHECK-NEXT: [[SHL35:%[0-9]+]]:_(s16) = G_SHL [[AND40]], [[C10]](s16)
524 ; CHECK-NEXT: [[SHL50:%[0-9]+]]:_(s16) = G_SHL [[AND56]], [[C10]](s16)
571 ; CHECK-NEXT: [[SHL65:%[0-9]+]]:_(s16) = G_SHL [[COPY7]], [[C10]](s16)
[all …]
H A Dlegalize-implicit-def-s1025.mir47 ; TAHITI-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
48 ; TAHITI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
99 ; TAHITI-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
146 ; TAHITI-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C10]](s32)
255 ; FIJI-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 10
256 ; FIJI-NEXT: [[LSHR10:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C10]](s16)
276 ; FIJI-NEXT: [[LSHR25:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C10]](s16)
H A Dlegalize-fptoui.mir220 ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
221 ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
284 ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
285 ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nnan G_FMINNUM_IEEE [[INT1]], [[C10]]
347 ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
348 ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
371 ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT3]], [[C10]]
/llvm-project-15.0.7/mlir/test/Interfaces/TilingInterface/
H A Dtile-using-interface.mlir18 // CHECK-DAG: %[[C10:.+]] = arith.constant 10 : index
25 // CHECK: %[[TS_Y:.+]] = affine.min #[[MAP0]](%[[IV0]])[%[[C10]], %[[M]]]
62 // CHECK-DAG: %[[C10:.+]] = arith.constant 10 : index
68 // CHECK: scf.for %[[IV0:[a-zA-Z0-9]+]] = %[[C0]] to %[[M]] step %[[C10]]
69 // CHECK: %[[TS_M:.+]] = affine.min #[[MAP0]](%[[IV0]])[%[[C10]], %[[M]]]
108 // CHECK-DAG: %[[C10:.+]] = arith.constant 10 : index
116 // CHECK: %[[TS_Y:.+]] = affine.min #[[MAP0]](%[[IV0]])[%[[C10]], %[[C128]]]
162 // CHECK-DAG: %[[C10:.+]] = arith.constant 10 : index
172 // CHECK: scf.for %[[IV0:[a-zA-Z0-9]+]] = %[[C0]] to %[[P]] step %[[C10]]
174 // CHECK: %[[TS_P:.+]] = affine.min #[[MAP0]](%[[IV0]])[%[[C10]], %[[P]]]
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/SparseTensor/
H A Dsparse_reshape.mlir20 // CHECK-CONV-DAG: %[[C10:.*]] = arith.constant 10 : index
28 // CHECK-CONV: %[[D:.*]] = arith.divui %[[X]], %[[C10]] : index
30 // CHECK-CONV: %[[R:.*]] = arith.remui %[[X]], %[[C10]] : index
59 // CHECK-CONV-DAG: %[[C10:.*]] = arith.constant 10 : index
67 // CHECK-CONV: %[[M:.*]] = arith.muli %[[X]], %[[C10]] : index
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dlto-visibility-inference.cpp54 struct C10 { struct
69 std::C7::C8 *c8, stdext::C9 *c9, other::C10 *c10) { in f()
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/infrastructure/
H A Dnolintbeginend.cpp78 class C10 { C10(int i); }; class
H A Dnolint.cpp48 class C10 { C10(int i); }; /* NOLINT */ class
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dcombine-udiv.mir82 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
97 …; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C10]](s16), [[C12]](s16), …
150 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
161 … = G_BUILD_VECTOR [[C8]](s16), [[C10]](s16), [[C10]](s16), [[C10]](s16), [[C10]](s16), [[C10]](s16…
212 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 25645
222 …; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C8]](s16), [[C10]](s16), […
314 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
326 …>) = G_BUILD_VECTOR [[C8]](s16), [[C10]](s16), [[C8]](s16), [[C8]](s16), [[C8]](s16), [[C8]](s16),…
H A Darm64-callingconv-ios.ll31 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
32 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C10]](s64)
66 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s8) = G_CONSTANT i8 99
78 ; CHECK-NEXT: G_STORE [[C10]](s8), [[PTR_ADD2]](p0) :: (store (s8) into stack + 4)
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dtile-indexed.mlir17 // TILE-10n25: %[[C10:.*]] = arith.constant 10 : index
18 // TILE-10n25: scf.for %[[J:.*]] = {{.*}} step %[[C10]]
54 // TILE-10n25-DAG: %[[C10:.*]] = arith.constant 10 : index
55 // TILE-10n25: scf.for %[[K:.*]] = {{.*}} step %[[C10]]
H A Dtile-to-foreach-thread.mlir16 // CHECK-DAG: %[[C10:.*]] = arith.constant 10 : index
18 // CHECK: scf.foreach_thread ({{.*}}) in (%[[C10]], %[[C20]]) -> (tensor<?x?xf32>) {
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dloop-range.mlir53 // CHECK: %[[C10:.*]] = arith.constant 10 : index
54 // CHECK: scf.for %[[J:.*]] = %[[C0]] to %[[C10]] step %[[C1]] {
86 // CHECK: %[[C10:.*]] = arith.constant 10 : index
88 // CHECK: %[[I1:.*]] = arith.addi %[[ARG2]], %[[C10]] : index
/llvm-project-15.0.7/mlir/test/Transforms/
H A Dparallel-loop-collapsing.mlir32 // CHECK-DAG: [[C10:%.*]] = arith.constant 10 : index
43 // CHECK: [[V2:%.*]] = arith.muli [[V0]], [[C10]] : index
/llvm-project-15.0.7/clang/test/Coverage/
H A Dast-print-temp-class.cpp26 template<typename T = int> class C10 {}; class
/llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/
H A Dexact-exit-count-more-precise.ll62 %C10 = icmp slt i1 undef, undef
63 br i1 %C10, label %BB, label %exit
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvec_extract.ll119 %C10 = icmp ule i1 false, false
121 %B = sdiv i1 %C10, %C3
/llvm-project-15.0.7/clang/test/Parser/
H A Dcxx2a-concept-declaration.cpp67 template<typename T> concept A::C10 = false;
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dms-uuid.cpp95 uuid("000000A0-0000-0000-C000-000000000049")] class C10;
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-cc-ext-vec-abi.ll72 ; ASM32-DAG: lwz [[REG11:[0-9]+]], L..C10(2)
106 ; ASM64-DAG: ld [[REG11:[0-9]+]], L..C10(2)
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td225 def C10 : Ri< 10, "C10">;
309 def C10_C11 : Rdi<10, "C10", [C10, C11]>;

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