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Searched refs:ByteVT (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1112 if (TLI.isShuffleMaskLegal(ShuffleMask, ByteVT)) { in ExpandBSWAP()
1114 SDValue Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Node->getOperand(0)); in ExpandBSWAP()
1115 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT), ShuffleMask); in ExpandBSWAP()
1157 if (TLI.isShuffleMaskLegal(BSWAPMask, ByteVT) && in ExpandBITREVERSE()
1158 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) || in ExpandBITREVERSE()
1159 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) && in ExpandBITREVERSE()
1160 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) && in ExpandBITREVERSE()
1161 TLI.isOperationLegalOrCustomOrPromote(ISD::AND, ByteVT) && in ExpandBITREVERSE()
1162 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, ByteVT)))) { in ExpandBITREVERSE()
1165 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT), in ExpandBITREVERSE()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp13127 VT, DAG.getNode(X86ISD::PALIGNR, DL, ByteVT, DAG.getBitcast(ByteVT, Hi), in lowerShuffleAsByteRotateAndPermute()
13128 DAG.getBitcast(ByteVT, Lo), in lowerShuffleAsByteRotateAndPermute()
13488 Lo = DAG.getBitcast(ByteVT, Lo); in lowerShuffleAsByteRotate()
13489 Hi = DAG.getBitcast(ByteVT, Hi); in lowerShuffleAsByteRotate()
13504 assert(ByteVT == MVT::v16i8 && in lowerShuffleAsByteRotate()
31438 SDValue ByteOp = DAG.getBitcast(ByteVT, Op0); in LowerVectorCTPOP()
38547 Res = CanonicalizeShuffleInput(ByteVT, V1); in combineX86ShuffleChain()
38577 MVT ByteVT = MVT::v16i8; in combineX86ShuffleChain() local
38578 V1 = CanonicalizeShuffleInput(ByteVT, V1); in combineX86ShuffleChain()
38579 V2 = CanonicalizeShuffleInput(ByteVT, V2); in combineX86ShuffleChain()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp16227 EVT ByteVT = in LowerSVEIntrinsicEXT() local
16231 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, ByteVT, N->getOperand(1)); in LowerSVEIntrinsicEXT()
16232 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, ByteVT, N->getOperand(2)); in LowerSVEIntrinsicEXT()
16236 SDValue EXT = DAG.getNode(AArch64ISD::EXT, dl, ByteVT, Op0, Op1, Op2); in LowerSVEIntrinsicEXT()