| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/ |
| H A D | buildpairf64-extractelementf64-implicit-sp.ll | 18 ; FPXX-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
22 ; NO-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}
23 ; NO-IMPLICIT-SP-NOT: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
|
| H A D | shrink-wrap-buildpairf64-extractelementf64.mir | 39 # CHECK-NEXT: BuildPairF64
42 $d0 = BuildPairF64 $zero, $zero
74 $d0 = BuildPairF64 $zero, $zero, implicit $sp
|
| H A D | 2013-11-18-fp64-const0.ll | 10 ; of BuildPairF64 instead of BuildPairF64_64.
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | sitofp_and_uitofp.mir | 81 ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 [[COPY]], [[LUi]]
84 ; FP32: [[BuildPairF64_1:%[0-9]+]]:afgr64 = BuildPairF64 [[ORi]], [[LUi1]]
|
| H A D | float_constants.mir | 48 ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 [[ORi1]], [[ORi]]
|
| H A D | float_args.mir | 105 ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 [[COPY]], [[COPY1]]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | double-bitmanip-dagcombines.ll | 18 ; RISCVISD::SplitF64/BuildPairF64 used for RV32IFD.
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 176 case Mips::BuildPairF64: in processFunctionAfterISel()
785 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL, in trySelect()
|
| H A D | MipsISelLowering.h | 150 BuildPairF64, enumerator
|
| H A D | MipsInstrFPU.td | 50 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
776 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
|
| H A D | MipsInstructionSelector.cpp | 618 STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, in select()
|
| H A D | MipsSEFrameLowering.cpp | 139 case Mips::BuildPairF64: in expandInstr()
|
| H A D | MipsSEInstrInfo.cpp | 464 case Mips::BuildPairF64: in expandPostRAPseudo()
|
| H A D | MipsScheduleP5600.td | 565 MTHC1_D64, BuildPairF64,
|
| H A D | MipsISelLowering.cpp | 205 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; in getTargetNodeName()
2368 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); in lowerFCOPYSIGN32()
2466 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); in lowerFABS32()
3710 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, in LowerFormalArguments()
|
| H A D | MipsFastISel.cpp | 400 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
|
| H A D | MipsSEISelLowering.cpp | 1191 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi); in lowerLOAD()
1237 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi); in lowerBITCAST()
|
| H A D | MipsScheduleGeneric.td | 868 def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs BuildPairF64,
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 41 BuildPairF64, enumerator
|
| H A D | RISCVInstrInfoD.td | 25 def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>;
|
| H A D | RISCVISelLowering.cpp | 8844 if (Op0->getOpcode() == RISCVISD::BuildPairF64) in PerformDAGCombine()
10768 return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi); in unpackF64OnRV32DSoftABI()
11443 RetValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, RetValue, in LowerCall()
11609 NODE_NAME_CASE(BuildPairF64) in getTargetNodeName()
|