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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.h28 BitVector getAliasedBits(const MCRegisterInfo &RegInfo,
29 const BitVector &SourceBits);
44 const BitVector &ReservedReg,
51 const BitVector &sourceBits() const { return SourceBits; } in sourceBits()
54 const BitVector &aliasedBits() const { return AliasedBits; } in aliasedBits()
70 BitVector SourceBits;
71 BitVector AliasedBits;
79 const BitVector &ReservedReg);
98 const BitVector ReservedReg;
99 const BitVector EmptyRegisters;
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H A DMCInstrDescView.h100 const BitVector *getUnique(BitVector &&BV) const;
103 mutable std::vector<std::unique_ptr<BitVector>> Cache;
136 bool hasAliasingRegisters(const BitVector &ForbiddenRegisters) const;
140 const BitVector &ForbiddenRegisters) const;
161 const BitVector &ImplDefRegs; // The set of aliased implicit def registers.
162 const BitVector &ImplUseRegs; // The set of aliased implicit use registers.
163 const BitVector &AllDefRegs; // The set of all aliased def registers.
164 const BitVector &AllUseRegs; // The set of all aliased use registers.
168 SmallVector<Variable, 4> Variables, const BitVector *ImplDefRegs,
169 const BitVector *ImplUseRegs, const BitVector *AllDefRegs,
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H A DRegisterAliasing.cpp14 BitVector getAliasedBits(const MCRegisterInfo &RegInfo, in getAliasedBits()
15 const BitVector &SourceBits) { in getAliasedBits()
16 BitVector AliasedBits(RegInfo.getNumRegs()); in getAliasedBits()
32 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg, in RegisterAliasingTracker()
49 const MCRegisterInfo &RegInfo, const BitVector &SourceBits) { in FillOriginAndAliasedBits()
61 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg) in RegisterAliasingTrackerCache()
82 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs) { in debugString()
H A DMCInstrDescView.cpp83 const BitVector *BitVectorCache::getUnique(BitVector &&BV) const { in getUnique()
87 Cache.push_back(std::make_unique<BitVector>()); in getUnique()
96 const BitVector *ImplDefRegs, in Instruction()
98 const BitVector *AllDefRegs, in Instruction()
99 const BitVector *AllUseRegs) in Instruction()
168 BitVector ImplDefRegs = RATC.emptyRegisters(); in create()
169 BitVector ImplUseRegs = RATC.emptyRegisters(); in create()
170 BitVector AllDefRegs = RATC.emptyRegisters(); in create()
171 BitVector AllUseRegs = RATC.emptyRegisters(); in create()
212 static bool anyCommonExcludingForbidden(const BitVector &A, const BitVector &B, in anyCommonExcludingForbidden()
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H A DParallelSnippetGenerator.cpp120 const BitVector &ForbiddenRegisters) { in generateSnippetUsingStaticRenaming()
124 std::vector<BitVector> PossibleRegsForVar; in generateSnippetUsingStaticRenaming()
129 BitVector PossibleRegs = Op.getRegisterAliasing().sourceBits(); in generateSnippetUsingStaticRenaming()
149 for (BitVector &OtherPossibleRegs : PossibleRegsForVar) { in generateSnippetUsingStaticRenaming()
159 InstructionTemplate Variant, const BitVector &ForbiddenRegisters) const { in generateCodeTemplates()
193 BitVector ImplicitUses(State.getRegInfo().getNumRegs()); in generateCodeTemplates()
194 BitVector ImplicitDefs(State.getRegInfo().getNumRegs()); in generateCodeTemplates()
210 BitVector Defs(State.getRegInfo().getNumRegs()); in generateCodeTemplates()
H A DSnippetGenerator.h66 const BitVector &ExtraForbiddenRegs) const;
80 const BitVector &ForbiddenRegisters) const = 0;
93 size_t randomBit(const BitVector &Vector);
103 const BitVector &ForbiddenRegs,
/llvm-project-15.0.7/bolt/include/bolt/Passes/
H A DLivenessAnalysis.h51 BitVector BV = *this->getStateAt(P); in scavengeRegAfter()
53 BitVector GPRegs(NumRegs, false); in scavengeRegAfter()
76 BitVector State(NumRegs, false); in getStartingStateAtBB()
86 return BitVector(NumRegs, false); in getStartingStateAtBB()
90 return BitVector(NumRegs, false); in getStartingStateAtPoint()
93 void doConfluence(BitVector &StateOut, const BitVector &StateIn) { in doConfluence()
97 BitVector computeNext(const MCInst &Point, const BitVector &Cur) { in computeNext()
98 BitVector Next = Cur; in computeNext()
101 BitVector Written = BitVector(NumRegs, false); in computeNext()
116 BitVector CSR = BitVector(NumRegs, false); in computeNext()
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H A DReachingDefOrUse.h45 BitVector BV = BitVector(this->BC.MRI->getNumRegs(), false); in isReachedBy()
81 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB) { in getStartingStateAtBB()
82 return BitVector(this->NumInstrs, false); in getStartingStateAtBB()
85 BitVector getStartingStateAtPoint(const MCInst &Point) { in getStartingStateAtPoint()
86 return BitVector(this->NumInstrs, false); in getStartingStateAtPoint()
89 void doConfluence(BitVector &StateOut, const BitVector &StateIn) { in doConfluence()
97 BitVector XClobbers = BitVector(this->BC.MRI->getNumRegs(), false); in doesXKillsY()
98 BitVector YClobbers = BitVector(this->BC.MRI->getNumRegs(), false); in doesXKillsY()
117 BitVector computeNext(const MCInst &Point, const BitVector &Cur) { in computeNext()
118 BitVector Next = Cur; in computeNext()
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H A DStackAllocationAnalysis.h28 friend class DataflowAnalysis<StackAllocationAnalysis, BitVector>;
44 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB);
46 BitVector getStartingStateAtPoint(const MCInst &Point);
48 void doConfluence(BitVector &StateOut, const BitVector &StateIn);
50 BitVector doKill(const MCInst &Point, const BitVector &StateIn,
53 void doConfluenceWithLP(BitVector &StateOut, const BitVector &StateIn,
56 BitVector computeNext(const MCInst &Point, const BitVector &Cur);
H A DStackReachingUses.h27 friend class DataflowAnalysis<StackReachingUses, BitVector, true>;
57 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB) { in getStartingStateAtBB()
58 return BitVector(NumInstrs, false); in getStartingStateAtBB()
61 BitVector getStartingStateAtPoint(const MCInst &Point) { in getStartingStateAtPoint()
62 return BitVector(NumInstrs, false); in getStartingStateAtPoint()
65 void doConfluence(BitVector &StateOut, const BitVector &StateIn) { in doConfluence()
72 BitVector computeNext(const MCInst &Point, const BitVector &Cur);
H A DReachingInsns.h26 friend class DataflowAnalysis<ReachingInsns<Backward>, BitVector, Backward>;
62 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB) { in getStartingStateAtBB()
63 return BitVector(this->NumInstrs, false); in getStartingStateAtBB()
66 BitVector getStartingStateAtPoint(const MCInst &Point) { in getStartingStateAtPoint()
67 return BitVector(this->NumInstrs, false); in getStartingStateAtPoint()
70 void doConfluence(BitVector &StateOut, const BitVector &StateIn) { in doConfluence()
74 BitVector computeNext(const MCInst &Point, const BitVector &Cur) { in computeNext()
75 BitVector Next = Cur; in computeNext()
H A DRegAnalysis.h31 BitVector getFunctionUsedRegsList(const BinaryFunction *Func);
37 BitVector getFunctionClobberList(const BinaryFunction *Func);
45 void getInstUsedRegsList(const MCInst &Inst, BitVector &RegSet,
51 void getInstClobberList(const MCInst &Inst, BitVector &KillSet) const;
55 bool isConservative(BitVector &Vec) const;
69 std::map<const BinaryFunction *, BitVector> RegsKilledMap;
72 std::map<const BinaryFunction *, BitVector> RegsGenMap;
83 void beConservative(BitVector &Result) const;
H A DDominatorAnalysis.h31 friend class DataflowAnalysis<DominatorAnalysis<Backward>, BitVector,
118 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB) { in getStartingStateAtBB()
122 return BitVector(this->NumInstrs, false); in getStartingStateAtBB()
124 return BitVector(this->NumInstrs, false); in getStartingStateAtBB()
125 return BitVector(this->NumInstrs, true); in getStartingStateAtBB()
128 BitVector getStartingStateAtPoint(const MCInst &Point) { in getStartingStateAtPoint()
129 return BitVector(this->NumInstrs, true); in getStartingStateAtPoint()
132 void doConfluence(BitVector &StateOut, const BitVector &StateIn) { in doConfluence()
136 BitVector computeNext(const MCInst &Point, const BitVector &Cur) { in computeNext()
137 BitVector Next = Cur; in computeNext()
H A DStackAvailableExpressions.h27 friend class DataflowAnalysis<StackAvailableExpressions, BitVector>;
41 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB);
42 BitVector getStartingStateAtPoint(const MCInst &Point);
43 void doConfluence(BitVector &StateOut, const BitVector &StateIn);
47 BitVector computeNext(const MCInst &Point, const BitVector &Cur);
H A DRegReAssign.h21 BitVector ClassicRegs;
22 BitVector CalleeSaved;
23 BitVector ClassicCSR;
24 BitVector ExtendedCSR;
25 BitVector GPRegs;
/llvm-project-15.0.7/bolt/lib/Passes/
H A DStackAvailableExpressions.cpp48 BitVector
53 return BitVector(NumInstrs, false); in getStartingStateAtBB()
54 return BitVector(NumInstrs, true); in getStartingStateAtBB()
57 BitVector
59 return BitVector(NumInstrs, true); in getStartingStateAtPoint()
62 void StackAvailableExpressions::doConfluence(BitVector &StateOut, in doConfluence()
63 const BitVector &StateIn) { in doConfluence()
95 BitVector XClobbers = BitVector(BC.MRI->getNumRegs(), false); in doesXKillsY()
96 BitVector YClobbers = BitVector(BC.MRI->getNumRegs(), false); in doesXKillsY()
110 BitVector StackAvailableExpressions::computeNext(const MCInst &Point, in computeNext()
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H A DRegAnalysis.cpp46 BitVector RegsKilled = getFunctionClobberList(Func); in RegAnalysis()
55 BitVector RegsGen = getFunctionUsedRegsList(Func); in RegAnalysis()
91 const BitVector &RegsKilled = Iter->second; in RegAnalysis()
98 const BitVector &RegsUsed = RegsGenMap.find(Func)->second; in RegAnalysis()
109 void RegAnalysis::beConservative(BitVector &Result) const { in beConservative()
115 BitVector BV(BC.MRI->getNumRegs(), false); in beConservative()
127 bool RegAnalysis::isConservative(BitVector &Vec) const { in isConservative()
132 BitVector BV(BC.MRI->getNumRegs(), false); in isConservative()
192 BitVector &KillSet) const { in getInstClobberList()
197 BitVector UsedRegs = BitVector(BC.MRI->getNumRegs(), false); in getFunctionUsedRegsList()
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H A DStackAllocationAnalysis.cpp42 BitVector
44 return BitVector(this->NumInstrs, false); in getStartingStateAtBB()
47 BitVector
49 return BitVector(this->NumInstrs, false); in getStartingStateAtPoint()
52 void StackAllocationAnalysis::doConfluence(BitVector &StateOut, in doConfluence()
57 BitVector StackAllocationAnalysis::doKill(const MCInst &Point, in doKill()
58 const BitVector &StateIn, in doKill()
61 BitVector Next = StateIn; in doKill()
88 BitVector NewIn = StateIn; in doConfluenceWithLP()
95 BitVector StackAllocationAnalysis::computeNext(const MCInst &Point, in computeNext()
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/llvm-project-15.0.7/llvm/include/llvm/ADT/
H A DBitVector.h75 class BitVector {
344 BitVector &set() { in set()
424 BitVector &flip() { in flip()
502 BitVector &operator&=(const BitVector &RHS) {
519 BitVector &reset(const BitVector &RHS) { in reset()
545 static BitVector &apply(F &&f, BitVector &Out, BitVector const &Arg, in apply()
558 BitVector &operator|=(const BitVector &RHS) {
566 BitVector &operator^=(const BitVector &RHS) {
828 inline BitVector::size_type capacity_in_bytes(const BitVector &X) { in capacity_in_bytes()
835 BitVector V;
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/llvm-project-15.0.7/llvm/lib/Support/
H A DGlobPattern.cpp27 static Expected<BitVector> expand(StringRef S, StringRef Original) { in expand()
28 BitVector BV(256, false); in expand()
67 static Expected<BitVector> scan(StringRef &S, StringRef Original) { in scan()
73 return BitVector(); in scan()
76 return BitVector(256, true); in scan()
88 Expected<BitVector> BV = expand(Chars.substr(1), Original); in scan()
101 BitVector BV(256, false); in scan()
135 Expected<BitVector> BV = scan(S, Original); in create()
154 bool GlobPattern::matchOne(ArrayRef<BitVector> Pats, StringRef S) const { in matchOne()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegisterScavenging.h67 BitVector KillRegUnits, DefRegUnits;
68 BitVector TmpRegUnits;
136 BitVector getRegsAvailable(const TargetRegisterClass *RC);
203 void setUsed(const BitVector &RegUnits) { in setUsed()
206 void setUnused(const BitVector &RegUnits) { in setUnused()
215 void addRegUnits(BitVector &BV, MCRegister Reg);
218 void removeRegUnits(BitVector &BV, MCRegister Reg);
225 BitVector &Candidates,
H A DLiveRangeCalc.h63 BitVector Seen;
76 using EntryInfoMap = DenseMap<LiveRange *, std::pair<BitVector, BitVector>>;
130 MachineBasicBlock &MBB, BitVector &DefOnEntry,
131 BitVector &UndefOnEntry);
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses;
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
127 void getSubRegs(unsigned Reg, BitVector &SRs) const;
128 void expandReg(unsigned Reg, BitVector &Set) const;
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
130 BitVector &Uses) const;
146 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs()
151 void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const { in expandReg()
159 BitVector &Uses) const { in getDefsUses()
175 BitVector &Set = MO.isDef() ? Defs : Uses; in getDefsUses()
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/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DStackLifetime.h46 BitVector Begin;
49 BitVector End;
52 BitVector LiveIn;
55 BitVector LiveOut;
64 BitVector Bits;
113 BitVector InterestingAllocas;
169 static inline raw_ostream &operator<<(raw_ostream &OS, const BitVector &V) {
/llvm-project-15.0.7/llvm/utils/TableGen/GlobalISel/
H A DGIMatchTree.h269 BitVector RemainingInstrNodes;
270 BitVector RemainingEdges;
271 BitVector RemainingPredicates;
274 std::vector<BitVector> UnsatisfiedPredDepsForPred;
279 BitVector TraversableEdges;
280 BitVector TestablePredicates;
453 DenseMap<unsigned, BitVector> Partitions;
500 BitVector getPossibleLeavesForPartition(unsigned Idx) { in getPossibleLeavesForPartition()
560 std::vector<BitVector> TestedPredicates;
589 std::vector<BitVector> TraversedEdges;
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