Searched refs:Bit2 (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/mlir/unittests/TableGen/ |
| H A D | enums.td | 30 def Bit2 : I32BitEnumAttrCaseBit<"Bit2", 2>; 44 [Bit0, Bit1, Bit2, Bit3]>; 51 [Bit0, Bit1, Bit2, Bit3, Bit4, Bits0To3]> { 56 [Bit0, Bit1, Bit2, Bit3, Bit4, Bit5,
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| H A D | EnumsGenTest.cpp | 112 BitEnumWithGroup::Bit2 | BitEnumWithGroup::Bit4), in TEST() 127 BitEnumPrimaryGroup::Bit2 | BitEnumPrimaryGroup::Bit3), in TEST() 130 BitEnumPrimaryGroup::Bit2 | in TEST() 139 BitEnumPrimaryGroup::Bit2 | BitEnumPrimaryGroup::Bit3 | in TEST()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 361 uint16_t Bit2 = (VR2 == SelR) ? SelB : BitN; in operator ()() local 368 return Bit2 < W2; in operator ()() 370 if (W2 <= Bit2) in operator ()() 373 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2]; in operator ()()
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| /llvm-project-15.0.7/mlir/docs/ |
| H A D | OpDefinitions.md | 1398 def Bit2: BitEnumAttrCaseBit<"Bit2", 2>; 1402 [None, Bit0, Bit1, Bit2, Bit3]>; 1413 Bit2 = 4, 1461 if (4u == (4u & val)) { strs.push_back("Bit2"); } 1479 .Case("Bit2", 4)
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