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Searched refs:Bit1 (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/mlir/unittests/TableGen/
H A Denums.td29 def Bit1 : I32BitEnumAttrCaseBit<"Bit1", 1>;
44 [Bit0, Bit1, Bit2, Bit3]>;
51 [Bit0, Bit1, Bit2, Bit3, Bit4, Bits0To3]> {
56 [Bit0, Bit1, Bit2, Bit3, Bit4, Bit5,
64 def BitEnum64_1 : I64BitEnumAttrCaseBit<"Bit1", 1>;
H A DEnumsGenTest.cpp73 EXPECT_EQ(2u, static_cast<uint64_t>(BitEnum64_Test::Bit1)); in TEST()
85 EXPECT_EQ(stringifyBitEnum64_Test(BitEnum64_Test::Bit1), "Bit1"); in TEST()
87 stringifyBitEnum64_Test(BitEnum64_Test::Bit1 | BitEnum64_Test::Bit57), in TEST()
111 BitEnumWithGroup::Bit0 | BitEnumWithGroup::Bit1 | in TEST()
126 BitEnumPrimaryGroup::Bit0 | BitEnumPrimaryGroup::Bit1 | in TEST()
138 BitEnumPrimaryGroup::Bit0 | BitEnumPrimaryGroup::Bit1 | in TEST()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp360 uint16_t Bit1 = (VR1 == SelR) ? SelB : BitN; in operator ()() local
367 if (W1 <= Bit1) in operator ()()
373 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2]; in operator ()()
/llvm-project-15.0.7/mlir/docs/
H A DOpDefinitions.md1397 def Bit1: BitEnumAttrCaseBit<"Bit1", 1>;
1402 [None, Bit0, Bit1, Bit2, Bit3]>;
1412 Bit1 = 2,
1460 if (2u == (2u & val)) { strs.push_back("Bit1"); }
1478 .Case("Bit1", 2)