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Searched refs:BaseOps2 (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h167 ArrayRef<const MachineOperand *> BaseOps2,
H A DAArch64InstrInfo.cpp3300 ArrayRef<const MachineOperand *> BaseOps2, unsigned NumLoads, in shouldClusterMemOps() argument
3302 assert(BaseOps1.size() == 1 && BaseOps2.size() == 1); in shouldClusterMemOps()
3304 const MachineOperand &BaseOp2 = *BaseOps2.front(); in shouldClusterMemOps()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h648 ArrayRef<const MachineOperand *> BaseOps2,
H A DPPCInstrInfo.cpp2817 ArrayRef<const MachineOperand *> BaseOps2, unsigned NumLoads, in shouldClusterMemOps() argument
2820 assert(BaseOps1.size() == 1 && BaseOps2.size() == 1); in shouldClusterMemOps()
2822 const MachineOperand &BaseOp2 = *BaseOps2.front(); in shouldClusterMemOps()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp456 ArrayRef<const MachineOperand *> BaseOps2) { in memOpsHaveSameBasePtr() argument
460 if (BaseOps1.front()->isIdenticalTo(*BaseOps2.front())) in memOpsHaveSameBasePtr()
485 ArrayRef<const MachineOperand *> BaseOps2, in shouldClusterMemOps() argument
490 if (!BaseOps1.empty() && !BaseOps2.empty()) { in shouldClusterMemOps()
492 const MachineInstr &SecondLdSt = *BaseOps2.front()->getParent(); in shouldClusterMemOps()
493 if (!memOpsHaveSameBasePtr(FirstLdSt, BaseOps1, SecondLdSt, BaseOps2)) in shouldClusterMemOps()
495 } else if (!BaseOps1.empty() || !BaseOps2.empty()) { in shouldClusterMemOps()
3119 ArrayRef<const MachineOperand *> BaseOps2) { in memOpsHaveSameBaseOperands() argument
3120 if (BaseOps1.size() != BaseOps2.size()) in memOpsHaveSameBaseOperands()
3123 if (!BaseOps1[I]->isIdenticalTo(*BaseOps2[I])) in memOpsHaveSameBaseOperands()
H A DSIInstrInfo.h202 ArrayRef<const MachineOperand *> BaseOps2,
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1403 ArrayRef<const MachineOperand *> BaseOps2, in shouldClusterMemOps() argument