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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrFMA3Info.cpp144 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group() local
145 bool IsFMA3Opcode = ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) || in getFMA3Group()
146 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) || in getFMA3Group()
147 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF)); in getFMA3Group()
170 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3; in getFMA3Group()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td260 let BaseOpcode = "RECIP_D32";
272 let BaseOpcode = "RSQRT_D32";
283 let BaseOpcode = "LDC132";
287 let BaseOpcode = "SDC164";
298 let BaseOpcode = "LDC164";
302 let BaseOpcode = "SDC164";
311 let BaseOpcode = "c.f."#NAME;
316 let BaseOpcode = "c.un."#NAME;
321 let BaseOpcode = "c.eq."#NAME;
347 let BaseOpcode = "c.sf."#NAME;
[all …]
H A DMipsEVAInstrInfo.td61 string BaseOpcode = instr_asm;
79 string BaseOpcode = instr_asm;
96 string BaseOpcode = instr_asm;
114 string BaseOpcode = instr_asm;
130 string BaseOpcode = instr_asm;
144 string BaseOpcode = instr_asm;
170 string BaseOpcode = instr_asm;
H A DMipsDSPInstrInfo.td274 string BaseOpcode = instr_asm;
285 string BaseOpcode = instr_asm;
296 string BaseOpcode = instr_asm;
307 string BaseOpcode = instr_asm;
319 string BaseOpcode = instr_asm;
330 string BaseOpcode = instr_asm;
341 string BaseOpcode = instr_asm;
351 string BaseOpcode = instr_asm;
363 string BaseOpcode = instr_asm;
374 string BaseOpcode = instr_asm;
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H A DMipsInstrFPU.td288 let BaseOpcode = "c.f."#NAME;
293 let BaseOpcode = "c.un."#NAME;
298 let BaseOpcode = "c.eq."#NAME;
303 let BaseOpcode = "c.ueq."#NAME;
324 let BaseOpcode = "c.sf."#NAME;
342 let BaseOpcode = "c.lt."#NAME;
350 let BaseOpcode = "c.le."#NAME;
397 let BaseOpcode = "RECIP_D32";
407 let BaseOpcode = "RSQRT_D32";
608 let BaseOpcode = "LDC164";
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H A DMicroMips32r6InstrInfo.td616 string BaseOpcode = opstr;
666 string BaseOpcode = opstr;
679 string BaseOpcode = opstr;
690 string BaseOpcode = opstr;
702 string BaseOpcode = opstr;
724 string BaseOpcode = opstr;
737 string BaseOpcode = opstr;
746 string BaseOpcode = opstr;
791 string BaseOpcode = opstr;
805 string BaseOpcode = opstr;
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H A DMipsDSPInstrFormats.td13 // Instructions with the same BaseOpcode and isNVStore values form a row.
14 let RowFields = ["BaseOpcode"];
49 string BaseOpcode = opstr;
H A DMipsInstrFormats.td42 // Instructions with the same BaseOpcode and isNVStore values form a row.
43 let RowFields = ["BaseOpcode"];
56 // Instructions with the same BaseOpcode and isNVStore values form a row.
57 let RowFields = ["BaseOpcode"];
119 string BaseOpcode = opstr;
H A DMips32r6InstrFormats.td17 // Instructions with the same BaseOpcode and isNVStore values form a row.
18 let RowFields = ["BaseOpcode"];
29 string BaseOpcode = opstr;
H A DMicroMipsInstrInfo.td221 let BaseOpcode = opstr;
232 let BaseOpcode = opstr;
274 string BaseOpcode = opstr;
290 string BaseOpcode = opstr;
588 let BaseOpcode = opstr;
593 let BaseOpcode = opstr;
600 let BaseOpcode = opstr;
607 let BaseOpcode = opstr;
H A DMicroMipsDSPInstrFormats.td13 string BaseOpcode = opstr;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DMIMGInstructions.td65 let PrimaryKey = ["BaseOpcode"];
212 MIMGBaseOpcode BaseOpcode;
263 let d16 = !if(BaseOpcode.HasD16, ?, 0);
274 let d16 = !if(BaseOpcode.HasD16, ?, 0);
286 let d16 = !if(BaseOpcode.HasD16, ?, 0);
304 let d16 = !if(BaseOpcode.HasD16, ?, 0);
317 let d16 = !if(BaseOpcode.HasD16, ?, 0);
338 let d16 = !if(BaseOpcode.HasD16, ?, 0);
495 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
1196 BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
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H A DAMDGPUInstrInfo.h49 unsigned BaseOpcode; member
84 getImageDimIntrinsicByBaseOpcode(unsigned BaseOpcode, unsigned Dim);
H A DAMDGPUInstCombineIntrinsic.cpp157 AMDGPU::getMIMGLZMappingInfo(ImageDimIntr->BaseOpcode)) { in simplifyAMDGCNImageIntrinsic()
174 AMDGPU::getMIMGMIPMappingInfo(ImageDimIntr->BaseOpcode)) { in simplifyAMDGCNImageIntrinsic()
191 AMDGPU::getMIMGBiasMappingInfo(ImageDimIntr->BaseOpcode)) { in simplifyAMDGCNImageIntrinsic()
209 AMDGPU::getMIMGOffsetMappingInfo(ImageDimIntr->BaseOpcode)) { in simplifyAMDGCNImageIntrinsic()
227 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in simplifyAMDGCNImageIntrinsic() local
228 AMDGPU::getMIMGBaseOpcodeInfo(ImageDimIntr->BaseOpcode); in simplifyAMDGCNImageIntrinsic()
230 if (BaseOpcode->HasD16) { in simplifyAMDGCNImageIntrinsic()
259 AMDGPU::getMIMGBaseOpcodeInfo(ImageDimIntr->BaseOpcode)->Sampler; in simplifyAMDGCNImageIntrinsic()
H A DSIInsertHardClauses.cpp127 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in getHardClauseType()
H A DAMDGPUInstructionSelector.cpp1552 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in selectImageIntrinsic() local
1556 unsigned IntrOpcode = Intr->BaseOpcode; in selectImageIntrinsic()
1569 if (!BaseOpcode->Sampler) in selectImageIntrinsic()
1592 if (BaseOpcode->Atomic) { in selectImageIntrinsic()
1598 const bool Is64Bit = BaseOpcode->AtomicX2 ? in selectImageIntrinsic()
1602 if (BaseOpcode->AtomicX2) { in selectImageIntrinsic()
1615 if (BaseOpcode->Store) { in selectImageIntrinsic()
1641 if (BaseOpcode->Atomic) in selectImageIntrinsic()
1710 if (BaseOpcode->AtomicX2) { in selectImageIntrinsic()
1740 if (BaseOpcode->Sampler) in selectImageIntrinsic()
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/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1369 emitByte(BaseOpcode, OS); in encodeInstruction()
1390 emitByte(BaseOpcode, OS); in encodeInstruction()
1397 emitByte(BaseOpcode, OS); in encodeInstruction()
1405 emitByte(BaseOpcode, OS); in encodeInstruction()
1418 emitByte(BaseOpcode, OS); in encodeInstruction()
1434 emitByte(BaseOpcode, OS); in encodeInstruction()
1450 emitByte(BaseOpcode, OS); in encodeInstruction()
1470 emitByte(BaseOpcode, OS); in encodeInstruction()
1480 emitByte(BaseOpcode, OS); in encodeInstruction()
1516 emitByte(BaseOpcode, OS); in encodeInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagon.td182 // Instructions with the same BaseOpcode and isNVStore values form a row.
183 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
198 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
210 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
222 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
234 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
246 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
258 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
340 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
348 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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H A DHexagonDepInstrInfo.td53 let BaseOpcode = "A2_add";
217 let BaseOpcode = "A2_addi";
303 let BaseOpcode = "A2_and";
344 let BaseOpcode = "A2_aslh";
588 let BaseOpcode = "A2_or";
632 let BaseOpcode = "A2_add";
649 let BaseOpcode = "A2_add";
832 let BaseOpcode = "A2_or";
847 let BaseOpcode = "A2_or";
860 let BaseOpcode = "A2_or";
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H A DHexagonPseudo.td168 let BaseOpcode = "call";
222 BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2 in
320 isBarrier = 1, BaseOpcode = "JMPret" in {
/llvm-project-15.0.7/llvm/docs/
H A DHowToUseInstrMappings.rst84 // instructions need to have same value for BaseOpcode field. It can be any
87 let RowFields = ["BaseOpcode"];
146 let BaseOpcode = "ADD";
154 let BaseOpcode = "ADD";
162 let BaseOpcode = "ADD";
169 ``PredRel`` is excluded from the analysis. ``BaseOpcode`` is another important
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp199 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, in getMIMGOpcode() argument
208 return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr; in getMIMGBaseOpcode()
219 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, in getAddrSizeMIMGOp() argument
222 unsigned AddrWords = BaseOpcode->NumExtraArgs; in getAddrSizeMIMGOp()
224 (BaseOpcode->LodOrClampOrMip ? 1 : 0); in getAddrSizeMIMGOp()
235 if (BaseOpcode->Gradients) { in getAddrSizeMIMGOp()
236 if ((IsA16 && !IsG16Supported) || BaseOpcode->G16) in getAddrSizeMIMGOp()
249 uint16_t BaseOpcode; member
259 uint16_t BaseOpcode; member
320 return Info ? Info->BaseOpcode : -1; in getMTBUFBaseOpcode()
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H A DAMDGPUBaseInfo.h301 MIMGBaseOpcode BaseOpcode; member
322 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
389 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
396 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
402 uint16_t BaseOpcode; member
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCInstrFormats.td113 string BaseOpcode = "";
500 let BaseOpcode = "ld_rs9";
511 let BaseOpcode = "ld_rs9";
537 let BaseOpcode = "ld_limm";
567 let BaseOpcode = "ld_rlimm";
591 let BaseOpcode = "st_rs9";
602 let BaseOpcode = "st_rs9";
627 let BaseOpcode = "st_limm";
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp852 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in convertMIMGInst() local
853 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in convertMIMGInst()
856 if (BaseOpcode->BVH) { in convertMIMGInst()
879 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); in convertMIMGInst()
910 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); in convertMIMGInst()

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