Searched refs:BaseOpB (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 103 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; in areMemAccessesTriviallyDisjoint() local
107 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
108 if (BaseOpA->isIdenticalTo(*BaseOpB)) { in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1200 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; in areMemAccessesTriviallyDisjoint() local
1204 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
1205 if (BaseOpA->isIdenticalTo(*BaseOpB)) { in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 5555 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; in areMemAccessesTriviallyDisjoint() local
5559 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
5560 if (BaseOpA->isIdenticalTo(*BaseOpB)) { in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1046 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; in areMemAccessesTriviallyDisjoint() local
1067 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, OffsetBIsScalable, in areMemAccessesTriviallyDisjoint()
1069 if (BaseOpA->isIdenticalTo(*BaseOpB) && in areMemAccessesTriviallyDisjoint()
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