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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Difcvt3.ll4 ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-BX
25 ; CHECK-V4-BX-LABEL: t1:
26 ; CHECK-V4-BX: @ %bb.0:
27 ; CHECK-V4-BX-NEXT: cmp r2, #7
28 ; CHECK-V4-BX-NEXT: cmpne r2, #1
29 ; CHECK-V4-BX-NEXT: addne r0, r1, r0
30 ; CHECK-V4-BX-NEXT: addeq r0, r0, r1
31 ; CHECK-V4-BX-NEXT: addeq r0, r0, #1
32 ; CHECK-V4-BX-NEXT: bx lr
H A Dnone-macho-v4t.ll7 ; BX can only take a register before v5t came along, so we must materialise
H A Dspeculation-hardening-sls.ll31 ; Make a very easy, very likely to predicate return (BX LR), to test that
/llvm-project-15.0.7/clang/test/Layout/
H A Dms-x86-primary-bases.cpp170 struct BX : B0X, B1X { int a; BX() : a(0xf000000B) {} virtual void g() { printf("B"); } }; in BX() struct
289 sizeof(BX)+
H A Dms-x86-aligned-tail-padding.cpp358 struct BX : B4X, virtual B2X, virtual B6X, virtual B3X { struct
360 BX() : a(0xf000000B) {} in BX() argument
474 sizeof(BX)+
H A Dms-x86-lazy-empty-nonvirtual-base.cpp583 struct BX : B2X, B1X, B3X, B4X, virtual B0X { struct
585 BX() : a(0x0000000B) { printf(" B = %p\n", this); } in BX() argument
731 sizeof(BX)+
/llvm-project-15.0.7/llvm/test/MC/X86/
H A Dintel-syntax.s451 shld DX, BX
452 shld DX, BX, CL
453 shld DX, BX, 1
454 shld [RAX], BX
455 shld [RAX], BX, CL
456 shrd DX, BX
457 shrd DX, BX, CL
458 shrd DX, BX, 1
459 shrd [RAX], BX
489 div AX, BX
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Doptimize-max-3.ll48 ; CHECK-NEXT: incl [[BX:%[a-z0-9]+]]
49 ; CHECK-NEXT: cmpl [[R14:%[a-z0-9]+]], [[BX]]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp695 uint16_t BX = im(2); in evaluate() local
696 RC[BX] = RC[BX].is(0) ? BT::BitValue::One in evaluate()
697 : RC[BX].is(1) ? BT::BitValue::Zero in evaluate()
704 uint16_t BX = im(2); in evaluate() local
707 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero) in evaluate()
708 .fill(W1+(W1-BX), W0, Zero); in evaluate()
709 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1); in evaluate()
/llvm-project-15.0.7/llvm/test/tools/llvm-exegesis/X86/
H A Danalysis-clustering-algorithms.test103 - 'ROL16ri BX BX i_0x1'
120 - 'BX=0x0'
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp190 {codeview::RegisterId::BX, X86::BX}, in initLLVMToSEHAndCVRegMapping()
763 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
775 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
812 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
813 return X86::BX; in getX86SubSuperRegisterOrZero()
848 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
884 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h105 ENTRY(BX) \
119 ENTRY(BX) \
H A DX86Disassembler.cpp2104 baseReg = MCOperand::createReg(X86::BX); in translateRMMemory()
2108 baseReg = MCOperand::createReg(X86::BX); in translateRMMemory()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td118 def BX : X86Reg<"bx", 3, [BL,BH]>;
146 def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;
411 (add AX, CX, DX, SI, DI, BX, BP, SP,
458 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;
478 (add AX, CX, DX, SI, DI, BX, BP, SP)>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td420 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
423 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
427 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
428 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedFalkorDetails.td1191 (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
1193 (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
1195 (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
1199 (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
1201 (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSLSHardening.cpp213 BuildMI(Entry, DebugLoc(), TII->get(ARM::BX)) in populateThunk()
H A DARMBaseInstrInfo.h651 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dthumb1.txt115 # BX
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfold-vector-select.ll17 <4 x i32> *%BW, <4 x i32> *%BX, <4 x i32> *%BY, <4 x i32> *%BZ,
134 store <4 x i32> %bx, <4 x i32>* %BX
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DTargetTest.cpp166 const unsigned Reg = X86::BX; in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td299 string BX = Bx; // Appendix of mask operations.
1747 def "_M_" # mti.BX : VPseudoUnaryNoMask<GPR, VR>,
1749 def "_M_" # mti.BX # "_MASK" : VPseudoMaskUnarySOutMask,
1759 def "_M_" # mti.BX : VPseudoUnaryNoMask<GPR, VR>,
1761 def "_M_" # mti.BX # "_MASK" : VPseudoMaskUnarySOutMask,
1772 def "_M_" # mti.BX : VPseudoUnaryNoMask<VR, VR, constraint>,
1796 def "_M_" # mti.BX : VPseudoNullaryPseudoM<BaseInst # "_MM">;
3048 (!cast<Instruction>(inst#"_M_"#mti.BX)
3060 (!cast<Instruction>(inst#"_M_"#mti.BX#"_MASK")
3379 (!cast<Instruction>(inst#"_M_"#mti.BX) $rs1,
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16-instructions.ll1013 ; CHECK-DAG: and.b16 [[BX:%rs[0-9]+]], [[BS]], -32768;
1014 ; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX]];
1067 ; CHECK-DAG: and.b16 [[BX:%rs[0-9]+]], [[BS]], -32768;
1068 ; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX]];
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dbasic-thumb-instructions.s202 @ BX
/llvm-project-15.0.7/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def63 CV_REGISTER(BX, 12)

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