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Searched refs:BSP (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-bitselect.ll7 ; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h178 BSP, enumerator
H A DAArch64SchedFalkorDetails.td914 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIF|BIT|BSL|BSP)v8i8$")>;
938 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIF|BIT|BSL|BSP)v16i8$")>;
H A DAArch64SchedCyclone.td502 // BIF,BIT,BSL,BSP
H A DAArch64SchedExynosM3.td668 def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>;
H A DAArch64SchedA57.td527 def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL|BSP)v16i8")>;
H A DAArch64SchedExynosM4.td811 def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>;
H A DAArch64SchedExynosM5.td849 def : InstRW<[M5WriteNALU2], (instregex "^(BIF|BIT|BSL|BSP)v")>;
H A DAArch64ISelLowering.cpp2124 MAKE_CASE(AArch64ISD::BSP) in getTargetNodeName()
7793 SDValue BSP = in LowerFCOPYSIGN() local
7794 DAG.getNode(AArch64ISD::BSP, DL, VecVT, SignMaskV, VecVal1, VecVal2); in LowerFCOPYSIGN()
7796 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, BSP); in LowerFCOPYSIGN()
7798 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, BSP); in LowerFCOPYSIGN()
7800 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, BSP); in LowerFCOPYSIGN()
7802 return BitCast(VT, BSP, DAG); in LowerFCOPYSIGN()
14713 return DAG.getNode(AArch64ISD::BSP, DL, VT, Sub, SubSibling, AddSibling); in tryCombineToBSL()
14741 return DAG.getNode(AArch64ISD::BSP, DL, VT, SDValue(BVN0, 0), in tryCombineToBSL()
19615 case AArch64ISD::BSP: in PerformDAGCombine()
H A DAArch64InstrInfo.td622 def AArch64bsp: SDNode<"AArch64ISD::BSP", SDT_AArch64trivec>;
4663 // Pseudo bitwise select pattern BSP.
4665 defm BSP : SIMDLogicalThreeVectorPseudo<TriOpFrag<(or (and node:$LHS, node:$MHS),
H A DSVEInstrFormats.td523 // Used to re-order the operands of BSP when lowering to BSL. BSP has the order: