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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmachine-outliner-bti.mir3 # AArch64 Branch Target Enforcement treats the BR and BLR indirect branch
4 # instructions differently. The BLR instruction can only target a BTI C
7 # transform a BLR instruction into a BR instruction.
35 BLR renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
38 BLR renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
41 …BLR killed renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
H A Dmachine-outliner-2fixup-blr-terminator.mir27 BLR $x20, implicit $sp
46 BLR $x20, implicit $sp
65 BLR $x20, implicit $sp
H A Dspeculation-hardening-sls-blr.mir6 # Check that the BLR SLS hardening transforms a BLR into a BL with operands as
H A Dexpand-blr-rvmarker-pseudo.mir37 # CHECK-NEXT: BLR $x0, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $l…
121 # CHECK-NEXT: BLR $x8, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implic…
H A Dchkstk.ll33 ; CHECK-REGSTATE-LARGE: frame-setup BLR killed $x16, implicit-def $lr, implicit $sp, implicit-def $…
H A Dspeculation-hardening.mir145 BLR killed renamable $x17, implicit-def dead $lr, implicit $sp
174 … BLR killed renamable $lr, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $w0
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dctrloops32.mir28 BLR implicit $lr, implicit $rm
54 BLR implicit $lr, implicit $rm
80 BLR implicit $lr, implicit $rm
106 BLR implicit $lr, implicit $rm
132 BLR implicit $lr, implicit $rm
158 BLR implicit $lr, implicit $rm
188 BLR implicit $lr, implicit $rm
214 BLR implicit $lr, implicit $rm
240 BLR implicit $lr, implicit $rm
266 BLR implicit $lr, implicit $rm
[all …]
H A Dearly-ret.mir24 BLR implicit $lr, implicit $rm, implicit killed $r3
30 ; CHECK: BLR implicit $lr, implicit $rm, implicit killed $r3
33 ; CHECK: BLR implicit $lr, implicit $rm, implicit killed $r3
63 BLR implicit $lr, implicit $rm, implicit killed $v2
74 ; CHECK: BLR implicit $lr, implicit $rm, implicit killed $v2
104 BLR implicit $lr, implicit $rm, implicit killed $v2
115 ; CHECK: BLR implicit $lr, implicit $rm, implicit killed $v2
136 BLR implicit $lr, implicit $rm
145 ; CHECK: BLR implicit $lr, implicit $rm
H A Daix-print-pc.mir22 BLR implicit $lr, implicit $rm, implicit killed $r3
26 BLR implicit $lr, implicit $rm, implicit killed $r3
H A Dearly-ret-verify.mir39 BLR implicit $lr, implicit $rm
59 ; CHECK: BLR implicit $lr, implicit $rm
H A Dquadint-return.ll19 ; CHECK-NEXT: BLR
H A Daix32-crsave.mir18 BLR implicit $lr, implicit $rm, implicit $r3
55 BLR implicit $lr, implicit $rm, implicit $r3
H A Difcvt.mir48 BLR implicit $lr, implicit $rm
H A Dsh-overflow.mir28 BLR implicit $lr, implicit $rm, implicit killed $r3
H A Dstack-coloring-vararg.mir160 BLR implicit $lr, implicit $rm
169 BLR implicit $lr, implicit $rm
H A Daix32-vector-vararg-fixed-callee.ll20 ; CHECK: BLR implicit $lr, implicit $rm, implicit $f1
H A Dkernel-fp-round.ll28 ; CHECK-P6-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
H A Daix32-vector-vararg-callee-split.ll23 ; CHECK: BLR implicit $lr, implicit $rm, implicit $v2
H A Daix32-vector-vararg-callee.ll33 ; CHECK: BLR implicit $lr, implicit $rm, implicit $v2
H A Daix-xcoff-reloc-symb.mir20 BLR implicit $lr, implicit $rm, implicit killed $r3
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SLSHardening.cpp111 case AArch64::BLR: in isBLR()
281 MachineInstr &BLR = *MBBI; in ConvertBLRToBL() local
282 assert(isBLR(BLR)); in ConvertBLRToBL()
286 switch (BLR.getOpcode()) { in ConvertBLRToBL()
287 case AArch64::BLR: in ConvertBLRToBL()
290 Reg = BLR.getOperand(0).getReg(); in ConvertBLRToBL()
292 RegIsKilled = BLR.getOperand(0).isKill(); in ConvertBLRToBL()
303 DebugLoc DL = BLR.getDebugLoc(); in ConvertBLRToBL()
366 BL->copyImplicitOps(MF, BLR); in ConvertBLRToBL()
367 MF.moveCallSiteInfo(&BLR, BL); in ConvertBLRToBL()
H A DAArch64SchedPredExynos.td27 // Identify BLR specifying the LR register as the indirect target register.
29 CheckAll<[CheckOpcode<[BLR]>,
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_trampoline_AArch64.S45 BLR X2
98 BLR X2
149 BLR X2
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Duaddo-8-16-bits.mir144 ; CHECK-NEXT: BLR renamable $x2, implicit-def dead $lr, implicit $sp, implicit $w0
148 ; CHECK-NEXT: BLR killed renamable $x2, implicit-def dead $lr, implicit $sp, implicit $w0
176 BLR renamable $x2, implicit-def dead $lr, implicit $sp, implicit $w0
180 BLR killed renamable $x2, implicit-def dead $lr, implicit $sp, implicit $w0
370 ; CHECK-NEXT: BLR renamable $x2, implicit-def dead $lr, implicit $sp, implicit $w0
388 ; CHECK-NEXT: BLR renamable $x2, implicit-def dead $lr, implicit $sp, implicit $w0
405 BLR renamable $x2, implicit-def dead $lr, implicit $sp, implicit $w0
421 BLR renamable $x2, implicit-def dead $lr, implicit $sp, implicit $w0
509 ; CHECK-NEXT: BLR renamable $x2, implicit-def dead $lr, implicit $sp, implicit $w0
541 BLR renamable $x2, implicit-def dead $lr, implicit $sp, implicit $w0
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCEarlyReturn.cpp60 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()

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