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Searched refs:BLENDV (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h28 CMP_MASK_CC,CMP_MASK_SCALAR_CC, VSHIFT, COMI, COMI_RM, BLENDV, BEXTRI, enumerator
344 X86_INTRINSIC_DATA(avx_blendv_pd_256, BLENDV, X86ISD::BLENDV, 0),
345 X86_INTRINSIC_DATA(avx_blendv_ps_256, BLENDV, X86ISD::BLENDV, 0),
377 X86_INTRINSIC_DATA(avx2_pblendvb, BLENDV, X86ISD::BLENDV, 0),
1320 X86_INTRINSIC_DATA(sse41_blendvpd, BLENDV, X86ISD::BLENDV, 0),
1321 X86_INTRINSIC_DATA(sse41_blendvps, BLENDV, X86ISD::BLENDV, 0),
1324 X86_INTRINSIC_DATA(sse41_pblendvb, BLENDV, X86ISD::BLENDV, 0),
H A DX86ISelLowering.h210 BLENDV, enumerator
H A DX86InstrFragmentsSIMD.td503 def X86Blendv : SDNode<"X86ISD::BLENDV",
H A DX86ISelLowering.cpp8490 case X86ISD::BLENDV: { in getFauxShuffleMask()
26814 case BLENDV: { in LowerINTRINSIC_WO_CHAIN()
28964 return DAG.getNode(X86ISD::BLENDV, DL, VT, Src, Sub, Src); in LowerABS()
33496 NODE_NAME_CASE(BLENDV) in getTargetNodeName()
41285 case X86ISD::BLENDV: { in SimplifyDemandedVectorEltsForTargetNode()
41790 case X86ISD::BLENDV: { in SimplifyDemandedBitsForTargetNode()
44271 if (Opcode != X86ISD::BLENDV && Opcode != ISD::VSELECT) in narrowVectorSelect()
44379 N->getOpcode() != X86ISD::BLENDV) || in combineVSelectToBLENDV()
44423 UI->getOpcode() != X86ISD::BLENDV) || in combineVSelectToBLENDV()
44445 if (U->getOpcode() == X86ISD::BLENDV) in combineVSelectToBLENDV()
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H A DX86ISelDAGToDAG.cpp1039 CurDAG->getNode(X86ISD::BLENDV, SDLoc(N), N->getValueType(0), in PreprocessISelDAG()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davx-select.ll61 ; If a X86ISD::BLENDV node appears before legalization, constant fold using (mask < 0) instead of l…
H A Dvselect-pcmp.ll8 ; The condition vector for BLENDV* only cares about the sign bit of each element.
9 ; So in these tests, if we generate BLENDV*, we should be able to remove the redundant cmp op.