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Searched refs:BH (Results 1 – 25 of 28) sorted by relevance

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/llvm-project-15.0.7/llvm/unittests/ObjectYAML/
H A DYAMLTest.cpp23 static void mapping(IO &IO, BinaryHolder &BH) { in mapping()
24 IO.mapRequired("Binary", BH.Binary); in mapping()
31 BinaryHolder BH; in TEST() local
35 YOut << BH; in TEST()
42 BinaryHolder BH; in TEST() local
45 Input >> BH; in TEST()
/llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/
H A Ddfaddsub.S15 #define BH r3 macro
80 EXPB = extractu(BH,#EXPBITS,#HI_MANTBITS)
128 B_POS = cmp.gt(BH,#-1)
154 BH = togglebit(BH,#31) define
166 BH = #1 define
170 BH = asl(BH,#31) define
174 if (p0.new) AH = xor(AH,BH)
316 p1 = cmp.gt(BH,#-1)
333 BH = ##0x80000000 define
336 if (!p0) AH = or(AH,BH)
[all …]
H A Ddffma.S19 #define BH r3 macro
147 TMP = xor(AH,BH)
454 BH = USR define
458 if (p0) BH = or(BH,BL)
461 USR = BH
475 BH = extractu(TMP,#2,#SR_ROUND_OFF) define
480 BH ^= lsr(AH,#31)
481 BL = BH
485 p0 = !cmp.eq(BH,#2)
607 BH = convert_df2sf(B) define
[all …]
H A Ddfdiv.S16 #define BH r3 macro
81 EXPBA = combine(BH,AH)
82 SIGN = xor(AH,BH)
88 #undef BH
211 #define BH r3 macro
402 EXPBA = combine(BH,AH)
404 BH = insert(TMP,#DF_EXPBITS+1,#DF_MANTBITS-32) // clear out hidden bit, sign bit define
408 if (P_TMP2) BH = or(BH,TMP) // if normal, add back in hidden bit
435 AH = xor(AH,BH)
450 AH = xor(AH,BH)
H A Ddfmul.S14 #define BH r3 macro
114 EXP1 = extractu(BH,#EXPBITS,#HI_MANTBITS)
119 TMP = xor(AH,BH)
400 BH = extract(BH,#1,#31) define
403 AH ^= asl(BH,#31)
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
10 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
29 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
/llvm-project-15.0.7/llvm/test/Demangle/
H A Dms-conversion-operators.test5 ??$?BH@TemplateOps@@QAEHXZ
47 ??$?BH@CompoundTypeOps@@QAE?AU?$Bar@U?$Foo@H@@@@XZ
H A Dinvalid-manglings.test153 ?foo@?$?BH@@QAEHXZ
155 ; CHECK-NEXT: ?foo@?$?BH@@QAEHXZ
H A Dms-string-literals.test237 ??_C@_01LLKFGJJG@?$BH?$AA@
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb2-ldrb-ldrh.s4 @ Thumb2 LDRS?[BH] are not valid when Rt == PC (these encodings are used for
/llvm-project-15.0.7/openmp/runtime/src/
H A Dkmp_alloc.cpp151 #define BH(p) ((bhead_t *)(p)) macro
499 ba = BH(((char *)b) + (b->bh.bb.bsize - (bufsize)size)); in bget()
500 bn = BH(((char *)ba) + size); in bget()
532 ba = BH(((char *)b) + b->bh.bb.bsize); in bget()
644 b = BH(buf - sizeof(bhead_t)); in bgetz()
679 b = BH(((char *)buf) - sizeof(bhead_t)); in bgetr()
753 KMP_DEBUG_ASSERT(BH((char *)b - b->bh.bb.bsize)->bb.prevfree == 0); in brel()
770 KMP_DEBUG_ASSERT(BH((char *)b - b->bh.bb.prevfree)->bb.bsize == in brel()
796 KMP_DEBUG_ASSERT(BH((char *)bn + bn->bh.bb.bsize)->bb.prevfree == in brel()
930 bn = BH(((char *)b) + len); in bpool()
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-exegesis/X86/
H A Danalysis-clustering-algorithms.test50 - 'ROL8ri BH BH i_0x1'
71 - 'BH=0x0'
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp186 {codeview::RegisterId::BH, X86::BH}, in initLLVMToSEHAndCVRegMapping()
763 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
764 return X86::BH; in getX86SubSuperRegisterOrZero()
775 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
812 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
848 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
884 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td61 def BH : X86Reg<"bh", 7>;
118 def BX : X86Reg<"bx", 3, [BL,BH]>;
391 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
397 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
399 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
457 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
470 (add AL, CL, DL, AH, CH, DH, BL, BH)> {
471 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
H A DREADME-X86-64.txt44 It's not possible to reference AH, BH, CH, and DH registers in an instruction
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1440 bits<2> BH;
1447 let Inst{19-20} = BH;
1461 let BH = 0;
1468 let BH = 0;
1476 let BH = 0;
1533 bits<2> BH;
1543 let Inst{19-20} = BH;
1562 let BH = 0;
1579 let Inst{19-20} = 0; // Unused (BH)
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleR52.td293 "tLDR[BH](r|i|spi|pci|pciASM)", "tLDR(r|i|spi|pci|pciASM)",
491 "RFE", "t2RFE", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
496 "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
497 "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
H A DARMScheduleSwift.td358 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
492 "t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
497 "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
498 "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfold-vector-select.ll13 <4 x i32> *%BG, <4 x i32> *%BH, <4 x i32> *%BI, <4 x i32> *%BJ,
118 store <4 x i32> %bh, <4 x i32>* %BH
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h83 ENTRY(BH) \
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN2.td1769 def : InstRW<[N2Write_2cyc_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]$")>;
2092 "^LDNT1S[BH]_ZZR_S_REAL$")>;
2129 def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_IMM_REAL$",
2149 def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW_REAL$",
2214 def : InstRW<[N2Write_4cyc_2L01_2V], (instregex "^SST1[BH]_S_IMM$",
2234 def : InstRW<[N2Write_4cyc_2L01_2V], (instregex "^SST1[BH]_S_[SU]XTW$",
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16-instructions.ll1009 ; CHECK-DAG: ld.param.b16 [[BH:%h[0-9]+]], [test_copysign_param_1];
1011 ; CHECK-DAG: mov.b16 [[BS:%rs[0-9]+]], [[BH]];
1063 ; CHECK-DAG: ld.param.b16 [[BH:%h[0-9]+]], [test_copysign_extended_param_1];
1065 ; CHECK-DAG: mov.b16 [[BS:%rs[0-9]+]], [[BH]];
/llvm-project-15.0.7/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def59 CV_REGISTER(BH, 8)
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp780 const unsigned ExegesisX86Target::kUnavailableRegisters[4] = {X86::AH, X86::BH,
/llvm-project-15.0.7/llvm/docs/TableGen/
H A Dindex.rst67 AH, AL, AX, BH, BL, BP, BPL, BX, CH, CL, CX, DH, DI, DIL, DL, DX, EAX, EBP, EBX,

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