| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.h | 430 BFM, // Insert a range of bits into a 32-bit word. enumerator
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| H A D | AMDGPUInstrInfo.td | 266 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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| H A D | SIInstructions.td | 2862 multiclass BFMPatterns <ValueType vt, PatFrag SHL, PatFrag ADD, InstSI BFM> {
2865 (BFM $a, $b)
2870 (BFM $a, (i32 0))
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| H A D | SIISelLowering.cpp | 5728 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT() local
5737 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
5742 DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
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| H A D | AMDGPUISelLowering.cpp | 4326 NODE_NAME_CASE(BFM) in getTargetNodeName()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | bitfield-insert.ll | 241 ; Bitfield insert where the second or operand is a better match to be folded into the BFM
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedCyclone.td | 173 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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| H A D | AArch64SchedTSV110.td | 409 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(S|U)?BFM(W|X)ri$")>;
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| H A D | AArch64SchedThunderX2T99.td | 556 def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "^BFM")>;
557 def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "(S|U)?BFM.*")>;
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| H A D | AArch64SchedThunderX3T110.td | 815 def : InstRW<[THX3T110Write_1Cyc_I0123], (instregex "^BFM")>;
816 def : InstRW<[THX3T110Write_1Cyc_I0123], (instregex "(S|U)?BFM.*")>;
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| H A D | AArch64SchedAmpere1.td | 981 def : InstRW<[Ampere1Write_1cyc_1B], (instregex "(S|U)?BFM(W|X)")>;
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| H A D | AArch64SchedA57.td | 165 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
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| H A D | AArch64SchedFalkorDetails.td | 1205 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(S|U)?BFM(W|X)ri$")>;
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| H A D | AArch64ISelDAGToDAG.cpp | 2223 SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64); in tryBitfieldExtractOp() local
2226 MVT::i32, SDValue(BFM, 0), SubReg)); in tryBitfieldExtractOp()
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| H A D | AArch64SchedA64FX.td | 943 def : InstRW<[A64FXWrite_4Cyc_NGI24], (instregex "^BFM")>;
944 def : InstRW<[A64FXWrite_1Cyc_GI24], (instregex "(S|U)?BFM.*")>;
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| H A D | AArch64SchedKryoDetails.td | 447 (instregex "(S|U)?BFM.*")>;
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| H A D | AArch64SchedNeoverseN2.td | 712 def : InstRW<[N2Write_2cyc_1M], (instregex "^BFM[WX]ri$")>;
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| H A D | AArch64InstrInfo.td | 2197 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 4027 MachineInstr &BFM = in selectMergeValues() local
4036 constrainSelectedInstRegOperands(BFM, TII, TRI, RBI); in selectMergeValues()
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