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Searched refs:BASE1 (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Damdgcn-load-offset-from-reg.ll49 ; SDAG-DAG: %[[BASE1:.*]]:sgpr_32 = COPY $sgpr1
51 ; SDAG-DAG: %[[BASE:.*]]:sgpr_64 = REG_SEQUENCE %[[BASE0]], %subreg.sub0, %[[BASE1]], %subreg.sub1
54 ; GISEL-DAG: %[[BASE1:.*]]:sreg_32 = COPY $sgpr1
56 ; GISEL-DAG: %[[BASE:.*]]:sreg_64 = REG_SEQUENCE %[[BASE0]], %subreg.sub0, %[[BASE1]], %subreg.sub1
71 ; SDAG-DAG: %[[BASE1:.*]]:sgpr_32 = COPY $sgpr1
73 ; SDAG-DAG: %[[BASE:.*]]:sgpr_64 = REG_SEQUENCE %[[BASE0]], %subreg.sub0, %[[BASE1]], %subreg.sub1
76 ; GISEL-DAG: %[[BASE1:.*]]:sreg_32 = COPY $sgpr1
78 ; GISEL-DAG: %[[BASE:.*]]:sreg_64 = REG_SEQUENCE %[[BASE0]], %subreg.sub0, %[[BASE1]], %subreg.sub1
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Ddecl-init-ref.cpp9 struct BASE1 { struct
13 class B : public BASE , public BASE1
H A Dambig-user-defined-conversions.cpp7 struct BASE1 { struct
11 struct B : public BASE, BASE1 {};
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-calling-convention-byref.ll31 ; CHECK-DAG: [[BASE1:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0
32 ; CHECK-DAG: $x0 = COPY [[BASE1]]
65 ; CHECK-DAG: [[BASE1:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0
67 ; CHECK-DAG: $x0 = COPY [[BASE1]]
109 ; CHECK-DAG: [[BASE1:%[0-9]+]]:gpr64common = ADDXri %stack.0, 0
112 ; CHECK-DAG: STRXui killed [[BASE1]], [[SP]], 0
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/modernize/
H A Dmacro-to-enum.cpp153 #define BASE1 0777 // octal macro
/llvm-project-15.0.7/llvm/test/Transforms/RewriteStatepointsForGC/
H A Drematerialize-derived-pointers.ll370 ; CHECK-NEXT: [[BASE1:%.*]] = call i32 addrspace(1)* @new_instance()
378 ; CHECK-NEXT: [[BASEPHI:%.*]] = phi i32 addrspace(1)* [ [[BASE1]], [[HERE]] ], [ [[BASE2]], [[TH…
413 ; CHECK-NEXT: [[BASE1:%.*]] = call i32 addrspace(1)* @new_instance()
421 ; CHECK-NEXT: [[BASEPHI:%.*]] = phi i32 addrspace(1)* [ [[BASE1]], [[HERE]] ], [ [[BASE2]], [[TH…
H A Dscalar-base-vector.ll17 ; CHECK-NEXT: [[PHI:%.*]] = phi i8 addrspace(1)* [ [[BASE1:%.*]], [[ENTRY:%.*]] ], [ [[BASE21]],…
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dforked-pointers.ll20 ; CHECK-NEXT: [[BASE1_FR:%.*]] = freeze float* [[BASE1:%.*]]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcodegen-prepare-addrmode-sext.ll311 ; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to ptr
312 ; CHECK: [[FULL1:%[a-zA-Z_0-9-]+]] = getelementptr i8, ptr [[BASE1]], i64 48
/llvm-project-15.0.7/llvm/test/Transforms/LoopIdiom/
H A Dbasic.ll47 ; CHECK-NEXT: [[BASE1:%.*]] = bitcast i16* [[BASE:%.*]] to i8*
49 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 2 [[BASE1]], i8 0, i64 [[TMP0]], i1 fals…
114 ; CHECK-NEXT: [[BASE1:%.*]] = bitcast i32* [[BASE:%.*]] to i8*
119 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 4 [[BASE1]], i8 1, i64 [[TMP0]], i1 fals…