Searched refs:Arrange (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ |
| H A D | sink-alloca.ll | 29 ; Arrange for there to be a single use of %argmem by returning it.
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| /llvm-project-15.0.7/llvm/lib/Support/Windows/ |
| H A D | Process.inc | 464 // Arrange to call srand once when this function is first used, and
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8470 SDValue Arrange = DAG.getVectorShuffle(WideVT, dl, Wide, ShuffleSrc2, ShuffV); in LowerINT_TO_FPVector() local
8474 Arrange = DAG.getBitcast(IntermediateVT, Arrange); in LowerINT_TO_FPVector()
8480 Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange, in LowerINT_TO_FPVector()
8483 Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange); in LowerINT_TO_FPVector()
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| /llvm-project-15.0.7/llvm/test/Transforms/SROA/ |
| H A D | basictest.ll | 1338 ; Arrange (via control flow) to have unmerged stores of a particular width to
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