| /llvm-project-15.0.7/mlir/test/ |
| H A D | CMakeLists.txt | 27 "If set, arch-specific Arm integration tests are run with an emulator.") 29 … "If arch-specific Arm integration tests run emulated, pass these as parameters to the emulator.") 31 "If arch-specific Arm integration tests run emulated, use this Arm native lli.") 33 …"If arch-specific Arm integration tests run emulated, find Arm native utility libraries in this di… 37 option(MLIR_RUN_ARM_SVE_TESTS "Run Arm SVE tests.")
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| /llvm-project-15.0.7/llvm/test/tools/llvm-objdump/ELF/ARM/ |
| H A D | unknown-instr-resync.test | 4 # sense for the Arm instruction set encoding. 7 # symbols as in Arm state, with the one in the middle unknown, and we 9 # any Arm instruction.
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | HowToCrossCompileBuiltinsOnArm.rst | 2 How to Cross Compile Compiler-rt Builtins For Arm 9 of compiler-rt for an Arm target, from an x86_64 Linux machine. 11 While this document concentrates on Arm and Linux the general principles should 55 Building compiler-rt builtins for Arm 83 information to generate code for the Arm architecture we are targeting. We will 84 need to select the Arm target, select the Armv7-A architecture and choose 85 between using Arm or Thumb. 169 Arm architecture not given 192 Arm Soft-Float Target 194 The instructions for the Arm hard-float target can be used for the soft-float [all …]
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| H A D | UserGuides.rst | 225 Notes on cross-building and testing the compiler-rt builtins for Arm.
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| H A D | GettingInvolved.rst | 168 * - Scalable Vectors and Arm SVE 255 submitting talks; and other general LLVM-related topics. Arm/AArch64
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| H A D | DiscourseMigrationGuide.md | 57 <tr><td>Code Generation - Arm</td><td>[email protected]</td></tr>
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| /llvm-project-15.0.7/lldb/docs/use/ |
| H A D | qemu-testing.rst | 16 with Arm or AArch64, but support for other architectures can be added easily. 53 **Example:** Build QEMU binaries and Arm/AArch64 Linux kernel image 76 Run QEMU Arm or AArch64 system emulation using run-qemu.sh 100 **Example:** Run QEMU Arm or AArch64 system emulation using run-qemu.sh
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| /llvm-project-15.0.7/lldb/source/Plugins/Architecture/ |
| H A D | CMakeLists.txt | 1 add_subdirectory(Arm)
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| /llvm-project-15.0.7/libc/AOR_v20.02/ |
| H A D | README.md | 1 This directory contains Arm's contribution of their optimized routines as
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| /llvm-project-15.0.7/llvm/test/MC/MachO/ARM/ |
| H A D | darwin-Thumb-reloc.s | 31 @ CHECK: CpuType: Arm (0xC)
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| H A D | darwin-ARM-reloc.s | 30 @ CHECK: CpuType: Arm (0xC)
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| /llvm-project-15.0.7/lldb/source/Plugins/ObjectFile/PDB/ |
| H A D | ObjectFilePDB.cpp | 64 case PDB_Machine::Arm: in GetArchitecture()
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| /llvm-project-15.0.7/mlir/include/mlir/Dialect/ArmSVE/ |
| H A D | ArmSVE.td | 26 let summary = "Basic dialect to target Arm SVE architectures"; 28 This dialect contains the definitions necessary to target specific Arm SVE
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| /llvm-project-15.0.7/llvm/include/llvm/BinaryFormat/ |
| H A D | Minidump.h | 152 } Arm; member
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| /llvm-project-15.0.7/llvm/test/tools/llvm-readobj/MachO/ |
| H A D | file-headers.test | 141 # ARM-NEXT: CpuType: Arm (0xC)
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| /llvm-project-15.0.7/llvm/unittests/ObjectYAML/ |
| H A D | MinidumpYAMLTest.cpp | 58 EXPECT_EQ(0x05060708u, SysInfo.CPU.Arm.CPUID); in TEST()
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| /llvm-project-15.0.7/llvm/tools/llvm-pdbutil/ |
| H A D | PdbYaml.cpp | 38 io.enumCase(Value, "Arm", PDB_Machine::Arm); in enumeration()
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| /llvm-project-15.0.7/llvm/include/llvm/DebugInfo/PDB/ |
| H A D | PDBTypes.h | 130 Arm = 0x1C0, enumerator
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| /llvm-project-15.0.7/llvm/lib/DebugInfo/PDB/ |
| H A D | PDBExtras.cpp | 314 CASE_OUTPUT_ENUM_CLASS_NAME(PDB_Machine, Arm, OS) in operator <<()
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| /llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/ARM/ |
| H A D | select-costs.ll | 9 ; FIXME: The Arm cost model needs to be updated for SizeAndLatency.
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| /llvm-project-15.0.7/llvm/lib/ObjectYAML/ |
| H A D | MinidumpYAML.cpp | 341 IO.mapOptional("CPU", Info.CPU.Arm); in streamMapping()
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| /llvm-project-15.0.7/clang/lib/Headers/ |
| H A D | CMakeLists.txt | 25 # Headers shared by Arm and AArch64
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| /llvm-project-15.0.7/clang/docs/ |
| H A D | OffloadingDesign.rst | 21 as NVPTX, AMDGPU, X86_64, Arm, and PowerPC. Offloading code is generated by
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrCDE.td | 9 // This file describes the Arm CDE (Custom Datapath Extension) instruction set.
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| /llvm-project-15.0.7/mlir/include/mlir/Conversion/ |
| H A D | Passes.td | 134 let summary = "Convert Arm NEON structured ops to intrinsics";
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