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Searched refs:Allows (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/misc/
H A Dnon-private-member-variables-in-classes.rst20 Allows to completely ignore classes if **all** the member variables in that
25 Allows to ignore (not diagnose) **all** the member variables declared with
/llvm-project-15.0.7/mlir/include/mlir/Interfaces/
H A DInferIntRangeInterface.td20 Allows operations to participate in range analysis for scalar integer values by
/llvm-project-15.0.7/llvm/tools/llvm-objcopy/
H A DCommonOpts.td124 "with --regex. Allows using '*' to match any number of "
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Bufferization/Transforms/
H A DPasses.td269 "Allows returning/yielding new allocations from a block.">,
272 "Allows unknown (not bufferizable) ops in the input IR.">,
344 "Allows returning/yielding new allocations from a block.">,
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DLoadStoreVectorizer.cpp1324 bool Allows = TTI.allowsMisalignedMemoryAccesses(F.getParent()->getContext(), in accessIsMisaligned() local
1327 LLVM_DEBUG(dbgs() << "LSV: Target said misaligned is allowed? " << Allows in accessIsMisaligned()
1329 return !Allows || !Fast; in accessIsMisaligned()
/llvm-project-15.0.7/compiler-rt/lib/asan/
H A Dasan_flags.inc91 "Allows the users to work around the bug in Nvidia drivers prior to "
/llvm-project-15.0.7/mlir/include/mlir/Conversion/
H A DPasses.td921 "Allows llvm to reassociate floating-point reductions for speed">,
924 "Allows compiler to assume vector indices fit in 32-bit if that "
/llvm-project-15.0.7/lldb/bindings/python/
H A Dpython-extensions.swig293 '''Allows iterating over the children of an :py:class:`SBValue`.'''
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrFormats.td365 // Allows you to specify each bit of opcode
/llvm-project-15.0.7/libcxx/docs/DesignDocs/
H A DFileTimeType.rst438 * Allows implicit truncation to 64 bit integers.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ScheduleAtom.td20 let IssueWidth = 2; // Allows 2 instructions per scheduling group.
H A DX86InstrAVX512.td541 // Supports two different pattern operators for mask and unmasked ops. Allows
843 // Supports two different pattern operators for mask and unmasked ops. Allows
/llvm-project-15.0.7/lldb/source/Commands/
H A DOptions.td378 "injecting it into the local context. Allows declaration of persistent, "
1102 Desc<"Allows the PC to leave the current function.">;
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td476 // Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies
496 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty,
/llvm-project-15.0.7/mlir/include/mlir/IR/
H A DOpBase.td275 // Allows providing an alternative name and summary to an existing type def.
/llvm-project-15.0.7/flang/include/flang/Optimizer/Dialect/
H A DFIROps.td2795 An entry in a dispatch table. Allows a function symbol to be bound
/llvm-project-15.0.7/clang/docs/
H A DUsersManual.rst3154 Allows to disable all extra types and functions that are not native to the compiler.
/llvm-project-15.0.7/llvm/docs/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/
H A DAMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack.md1306 Allows a mixture of these where some bits come from one location storage and
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUDwarfExtensionsForHeterogeneousDebugging.rst1046 Allows a mixture of these where some bits come from one location storage and
H A DLangRef.rst4738 - ``i``: An integer constant (of target-specific width). Allows either a simple
4742 - ``X``: Allows an operand of any kind, no constraint whatsoever. Typically
/llvm-project-15.0.7/clang/include/clang/Driver/
H A DOptions.td6162 HelpText<"Allows assuming by-value parameters do not alias any other value. "