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Searched refs:AddrIdx (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
H A DMipsMCNaCl.h20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp118 int AddrIdx[MaxAddressRegs]; member
125 const MachineOperand &AddrRegNext = MI.getOperand(AddrIdx[i]); in hasSameBaseAddress()
695 AddrIdx[NumAddresses++] = in setMI()
698 AddrIdx[NumAddresses++] = in setMI()
701 AddrIdx[NumAddresses++] = in setMI()
704 AddrIdx[NumAddresses++] = in setMI()
707 AddrIdx[NumAddresses++] = in setMI()
710 AddrIdx[NumAddresses++] = in setMI()
713 AddrIdx[NumAddresses++] = in setMI()
716 AddrIdx[NumAddresses++] = in setMI()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp736 unsigned AddrIdx; in searchRange() local
737 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) && in searchRange()
738 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) || in searchRange()