Searched refs:Add3 (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/ |
| H A D | broadcast.ll | 40 %Add3 = add i64 %v1, %v2
50 store i64 %Add3, i64 *%idxS3, align 8
100 %Add3 = add i32 %v1, %v4
110 store i32 %Add3, i32 *%idxS3, align 8
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1821 SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64); in LowerUDIVREM64() local
1830 SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64); in LowerUDIVREM64()
1844 SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE); in LowerUDIVREM64()
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| H A D | AMDGPULegalizerInfo.cpp | 3605 auto Add3 = B.buildAdd(S64, MulHi3, One64); in legalizeUnsignedDIV_REM64Impl() local
3615 auto Add4 = B.buildAdd(S64, Add3, One64); in legalizeUnsignedDIV_REM64Impl()
3627 S64, B.buildICmp(CmpInst::ICMP_NE, S1, C6, Zero32), Add4, Add3); in legalizeUnsignedDIV_REM64Impl()
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