Searched refs:Add2 (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/ |
| H A D | broadcast.ll | 39 %Add2 = add i64 %v2, %v1
49 store i64 %Add2, i64 *%idxS2, align 8
99 %Add2 = add i32 %v5, %v1
109 store i32 %Add2, i32 *%idxS2, align 8
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| /llvm-project-15.0.7/llvm/unittests/Analysis/ |
| H A D | ScalarEvolutionTest.cpp | 408 Instruction *Add2 = BinaryOperator::CreateAdd(Mul1, Add1, "", EntryBB); in TEST_F() local
414 Mul1 = BinaryOperator::CreateMul(Add2, Add1, "", EntryBB); in TEST_F()
415 Add1 = Add2; in TEST_F()
416 Add2 = BinaryOperator::CreateAdd(Mul1, Add1, "", EntryBB); in TEST_F()
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| /llvm-project-15.0.7/llvm/tools/llvm-profgen/ |
| H A D | ProfiledBinary.h | 515 bool inlineContextEqual(uint64_t Add1, uint64_t Add2);
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1342 Register Add2 = MI.getOperand(1).getReg(); in matchPtrAddImmedChain() local
1348 MachineInstr *Add2Def = MRI.getVRegDef(Add2); in matchPtrAddImmedChain()
1379 unsigned AS = MRI.getType(Add2).getAddressSpace(); in matchPtrAddImmedChain()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1783 SDValue Add2 = DAG.getBitcast(VT, in LowerUDIVREM64() local
1786 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); in LowerUDIVREM64()
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| H A D | AMDGPULegalizerInfo.cpp | 3565 auto Add2 = B.buildMerge(S64, {Add2_Lo, Add2_Hi}); in legalizeUnsignedDIV_REM64Impl() local
3571 auto MulHi3 = B.buildUMulH(S64, Numer, Add2); in legalizeUnsignedDIV_REM64Impl()
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