Searched refs:Add1_Lo (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1765 SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo, in LowerUDIVREM64() local
1768 Mulhi1_Hi, Add1_Lo.getValue(1)); in LowerUDIVREM64()
1770 DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi})); in LowerUDIVREM64()
1779 SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo, in LowerUDIVREM64()
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| H A D | AMDGPULegalizerInfo.cpp | 3552 auto Add1_Lo = B.buildUAddo(S32, S1, RcpLo, MulHi1_Lo); in legalizeUnsignedDIV_REM64Impl() local
3553 auto Add1_Hi = B.buildUAdde(S32, S1, RcpHi, MulHi1_Hi, Add1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
3554 auto Add1 = B.buildMerge(S64, {Add1_Lo, Add1_Hi}); in legalizeUnsignedDIV_REM64Impl()
3563 auto Add2_Lo = B.buildUAddo(S32, S1, Add1_Lo, MulHi2_Lo); in legalizeUnsignedDIV_REM64Impl()
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