| /llvm-project-15.0.7/llvm/examples/OrcV2Examples/LLJITWithCustomObjectLinkingLayer/ |
| H A D | LLJITWithCustomObjectLinkingLayer.cpp | 60 int (*Add1)(int) = Add1Addr.toPtr<int(int)>(); in main() local
62 int Result = Add1(42); in main()
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| /llvm-project-15.0.7/llvm/examples/OrcV2Examples/LLJITDumpObjects/ |
| H A D | LLJITDumpObjects.cpp | 65 int (*Add1)(int) = Add1Addr.toPtr<int(int)>(); in main() local
67 int Result = Add1(42); in main()
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| /llvm-project-15.0.7/llvm/examples/HowToUseLLJIT/ |
| H A D | HowToUseLLJIT.cpp | 95 int (*Add1)(int) = Add1Addr.toPtr<int(int)>(); in main() local
97 int Result = Add1(42); in main()
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| /llvm-project-15.0.7/llvm/examples/OrcV2Examples/LLJITWithObjectCache/ |
| H A D | LLJITWithObjectCache.cpp | 73 int (*Add1)(int) = Add1Addr.toPtr<int(int)>(); in runJITWithCache() local
75 int Result = Add1(42); in runJITWithCache()
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| /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/ |
| H A D | broadcast.ll | 38 %Add1 = add i64 %v2, %v1
48 store i64 %Add1, i64 *%idxS1, align 8
98 %Add1 = add i32 %v3, %v1
108 store i32 %Add1, i32 *%idxS1, align 8
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| /llvm-project-15.0.7/llvm/unittests/Analysis/ |
| H A D | AliasAnalysisTest.cpp | 181 auto *Add1 = BinaryOperator::CreateAdd(Value, Value, "add", BB); in TEST_F() local
200 EXPECT_EQ(AA.getModRefInfo(Add1, MemoryLocation()), ModRefInfo::NoModRef); in TEST_F()
201 EXPECT_EQ(AA.getModRefInfo(Add1, None), ModRefInfo::NoModRef); in TEST_F()
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| H A D | ScalarEvolutionTest.cpp | 406 Instruction *Add1 = BinaryOperator::CreateAdd(Mul1, Trunc, "", EntryBB); in TEST_F() local
407 Mul1 = BinaryOperator::CreateMul(Add1, Trunc, "", EntryBB); in TEST_F()
408 Instruction *Add2 = BinaryOperator::CreateAdd(Mul1, Add1, "", EntryBB); in TEST_F()
414 Mul1 = BinaryOperator::CreateMul(Add2, Add1, "", EntryBB); in TEST_F()
415 Add1 = Add2; in TEST_F()
416 Add2 = BinaryOperator::CreateAdd(Mul1, Add1, "", EntryBB); in TEST_F()
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| /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/ |
| H A D | outer_loop_test2.ll | 39 ; CHECK: %[[Add1:.*]] = add nsw <4 x i32> %[[WideBVal]], %[[VecIndTr]]
40 ; CHECK: %[[AccumPhiNext]] = add nsw <4 x i32> %[[Add1]], %[[AccumPhi]]
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| /llvm-project-15.0.7/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | BasicValueFactory.h | 212 const llvm::APSInt &Add1(const llvm::APSInt &V) { in Add1() function
|
| /llvm-project-15.0.7/llvm/tools/llvm-profgen/ |
| H A D | ProfiledBinary.h | 515 bool inlineContextEqual(uint64_t Add1, uint64_t Add2);
|
| /llvm-project-15.0.7/llvm/unittests/IR/ |
| H A D | PatternMatch.cpp | 1303 Value *Add1 = IRB.CreateExtractValue(Add, 1); in TEST_F() local
1307 EXPECT_FALSE(match(Add1, m_ExtractValue<0>(m_Value()))); in TEST_F()
1308 EXPECT_TRUE(match(Add1, m_ExtractValue<1>(m_Value()))); in TEST_F()
1314 EXPECT_FALSE(match(Add1, m_WithOverflowInst(WOI))); in TEST_F()
1319 EXPECT_TRUE(match(Add1, m_ExtractValue<1>(m_WithOverflowInst(WOI)))); in TEST_F()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 3991 SDValue Add1 = ShiftAmt->getOperand(1); in tryShiftAmountMod() local
3993 auto *Add1C = dyn_cast<ConstantSDNode>(Add1); in tryShiftAmountMod()
4005 X = Add1; in tryShiftAmountMod()
4010 if (Add1.getOpcode() == ISD::TRUNCATE) { in tryShiftAmountMod()
4011 Add1 = Add1.getOperand(0); in tryShiftAmountMod()
4012 SubVT = Add1.getValueType(); in tryShiftAmountMod()
4019 X = CurDAG->getNode(ISD::ADD, DL, SubVT, Add1, Add0); in tryShiftAmountMod()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2914 SDValue Add1 = ShiftAmt->getOperand(1); in tryShiftAmountMod() local
2917 if (isIntImmediate(Add1, Add1Imm) && (Add1Imm % Size == 0)) { in tryShiftAmountMod()
2940 CurDAG->getMachineNode(NegOpc, DL, SubVT, Zero, Add1); in tryShiftAmountMod()
2960 CurDAG->getMachineNode(NotOpc, DL, SubVT, Zero, Add1); in tryShiftAmountMod()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1769 SDValue Add1 = DAG.getBitcast(VT, in LowerUDIVREM64() local
1773 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1); in LowerUDIVREM64()
1774 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
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| H A D | AMDGPULegalizerInfo.cpp | 3554 auto Add1 = B.buildMerge(S64, {Add1_Lo, Add1_Hi}); in legalizeUnsignedDIV_REM64Impl() local
3556 auto MulLo2 = B.buildMul(S64, NegDenom, Add1); in legalizeUnsignedDIV_REM64Impl()
3557 auto MulHi2 = B.buildUMulH(S64, Add1, MulLo2); in legalizeUnsignedDIV_REM64Impl()
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| H A D | SIISelLowering.cpp | 10835 SDValue Add1 = DAG.getNode(Opc, SL, VT, Op0, Op1); in reassociateScalarOps() local
10836 return DAG.getNode(Opc, SL, VT, Add1, Op2); in reassociateScalarOps()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1088 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), in performADDCombine() local
1090 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); in performADDCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13385 SDValue Add1 = in TryDistrubutionADDVecReduce() local
13387 return DAG.getNode(ISD::ADD, dl, VT, Add1, N1.getOperand(N1RedOp)); in TryDistrubutionADDVecReduce()
|