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Searched refs:ARMv7 (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfast-isel-pic.ll21 ; ARMv7: LoadGV
22 ; ARMv7: movw [[reg2:r[0-9]+]],
23 ; ARMv7: movt [[reg2]],
25 ; ARMv7-ELF: LoadGV
27 ; ARMv7-ELF: .LPC
50 ; ARMv7: LoadIndirectSymbol
51 ; ARMv7: movw r[[reg5:[0-9]+]],
52 ; ARMv7: movt r[[reg5]],
55 ; ARMv7-ELF: LoadIndirectSymbol
57 ; ARMv7-ELF: .LPC
[all …]
H A Dfpcmp_ueq.ll2 …e armv7-apple-darwin -mcpu=cortex-a8 -filetype asm -o - %s | FileCheck -check-prefix CHECK-ARMv7 %s
19 ; CHECK-ARMv7-LABEL: f7:
20 ; CHECK-ARMv7: vcmp.f32
21 ; CHECK-ARMv7: vmrs APSR_nzcv, fpscr
22 ; CHECK-ARMv7: movweq
23 ; CHECK-ARMv7-NOT: vmrs
24 ; CHECK-ARMv7: movwvs
H A Dreadcyclecounter.ll7 ; The performance monitor we're looking for is an ARMv7 extension. It should be
H A Durem-opt-size.ll8 ; pulled into the binary. The test uses ARMv7-M.
H A Dmemfunc.ll105 ; IOS (ARMv7) should 8-byte align, others should 4-byte align
H A Dbuild-attributes.ll491 ; Tag_CPU_arch 'ARMv7'
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Ddirective-arch_extension-idiv.s4 @ RUN: | FileCheck %s -check-prefix CHECK-ARMv7
46 @ CHECK-ARMv7: error: instruction requires: divide in ARM
51 @ CHECK-ARMv7: error: instruction requires: divide in ARM
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dinvalid-because-armv7.txt4 # ARMv7 triple, probably because the relevant instruction is v8, though there
H A Dinvalid-thumbv8.txt4 # but in ARMv7, all these instructions are valid
H A Dinvalid-armv8.txt4 # but in ARMv7, all these instructions are valid
H A Dinvalid-armv7.txt3 # This file is checking ARMv7 encodings which are globally invalid, usually due
/llvm-project-15.0.7/llvm/docs/
H A DCompilerWriterInfo.rst21 * `ARMv7-A Architecture Reference Manual <https://developer.arm.com/docs/ddi0406/latest>`_ This has…
23 * `ARMv7-M Architecture Reference Manual <https://developer.arm.com/docs/ddi0403/latest>`_ This cov…
H A DHowToBuildOnARM.rst19 on the ARMv6 and ARMv7 architectures and may be inapplicable to older chips.
H A DBigEndianNEON.rst15 …efers to A64 instructions throughout, but is almost applicable to the A32/ARMv7 instruction sets a…
H A DLangRef.rst16602 - Some machines, like GPUs or ARMv7 NEON, do not support subnormal values.
/llvm-project-15.0.7/libunwind/src/
H A DUnwindRegistersSave.S849 vstmia r0, {d0-d15} @ fstmiax is deprecated in ARMv7+ and now behaves like vstmia
H A DUnwindRegistersRestore.S743 vldmia r0, {d0-d15} @ fldmiax is deprecated in ARMv7+ and now behaves like vldmia
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp674 #define ARMv7 (1u << 8) macro
680 (ARMv4T | ARMv5T | ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | \
686 (ARMv5TE | ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
688 (ARMv5TEJ | ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
689 #define ARMV6_ABOVE (ARMv6 | ARMv6K | ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
690 #define ARMV6T2_ABOVE (ARMv6T2 | ARMv7 | ARMv7S | ARMv8)
691 #define ARMV7_ABOVE (ARMv7 | ARMv7S | ARMv8)
1080 if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7) in EmulatePOP()
13788 m_arm_isa = ARMv7; in SetArchitecture()
14120 if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM) in ALUWritePC()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARM.td437 // True if the subtarget supports Multiprocessing extension (ARMv7 only).
441 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
H A DARMInstrInfo.td4716 // Division Instructions (ARMv7-A with virtualization extension)
/llvm-project-15.0.7/clang/docs/
H A DUsersManual.rst3583 The support for ARM (specifically ARMv6 and ARMv7) is considered stable