Home
last modified time | relevance | path

Searched refs:ARG2 (Results 1 – 25 of 155) sorted by relevance

1234567

/llvm-project-15.0.7/polly/lib/External/isl/
H A Disl_align_params_templ.c16 __isl_keep ARG2 **obj2) in FN()
22 space2 = FN(ARG2,peek_space)(*obj2); in FN()
29 FN(ARG2,check_named_params)(*obj2) < 0) in FN()
31 *obj1 = FN(ARG1,align_params)(*obj1, FN(ARG2,get_space)(*obj2)); in FN()
32 *obj2 = FN(ARG2,align_params)(*obj2, FN(ARG1,get_space)(*obj1)); in FN()
38 *obj2 = FN(ARG2,free)(*obj2); in FN()
H A Disl_pw_pullback_templ.c16 #undef ARG2
17 #define ARG2 isl_multi_aff macro
26 #undef ARG2
27 #define ARG2 isl_pw_multi_aff macro
H A Disl_align_params_bin_templ.c3 #undef ARG2
4 #define ARG2 TYPE macro
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dloop-range.mlir18 // CHECK-SAME: (%[[ARG0:.*]]: {{.*}}, %[[ARG1:.*]]: {{.*}}, %[[ARG2:.*]]: {{.*}}
22 // CHECK: %[[I0:.*]] = arith.addi %[[ARG2]], %[[C0]] : index
23 // CHECK: %[[I1:.*]] = arith.addi %[[ARG2]], %[[ARG1]] : index
55 // CHECK: %[[I0:.*]] = arith.addi %[[ARG2]], %[[C0]] : index
56 // CHECK: %[[I1:.*]] = arith.addi %[[ARG2]], %[[ARG1]] : index
87 // CHECK: %[[I0:.*]] = arith.addi %[[ARG2]], %[[C0]] : index
88 // CHECK: %[[I1:.*]] = arith.addi %[[ARG2]], %[[C10]] : index
90 // CHECK: %[[I1:.*]] = arith.addi %[[ARG2]], %[[ARG1]] : index
121 // CHECK: %[[I0:.*]] = arith.addi %[[ARG2]], %[[C0]] : index
122 // CHECK: %[[I1:.*]] = arith.addi %[[ARG2]], %[[ARG1]] : index
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-sve-asm.ll8 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
9 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
19 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
20 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
30 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
31 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
41 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
42 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
52 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
63 ; CHECK: [[ARG2:%[0-9]+]]:ppr = COPY $p0
[all …]
/llvm-project-15.0.7/mlir/test/Transforms/
H A Dcontrol-flow-sink.mlir8 // CHECK-NEXT: %[[V0:.*]] = arith.subi %[[ARG2]], %[[ARG1]]
11 // CHECK-NEXT: %[[V2:.*]] = arith.subi %[[ARG1]], %[[ARG2]]
20 // CHECK-NEXT: %[[V2:.*]] = arith.addi %[[ARG2]], %[[ARG2]]
60 // CHECK-NEXT: test.region_if_yield %[[ARG2]]
68 // CHECK-NEXT: test.region_if_yield %[[ARG2]]
102 // CHECK-NEXT: %[[V1:.*]] = arith.subi %[[ARG1]], %[[ARG2]]
103 // CHECK-NEXT: %[[V2:.*]] = arith.addi %[[ARG1]], %[[ARG2]]
104 // CHECK-NEXT: %[[V3:.*]] = arith.subi %[[ARG2]], %[[ARG1]]
114 // CHECK-NEXT: test.region_if_yield %[[ARG2]]
141 // CHECK-NEXT: %[[V0:.*]] = arith.addi %[[ARG1]], %[[ARG2]]
[all …]
/llvm-project-15.0.7/mlir/test/IR/
H A Dslice.mlir22 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
23 // CHECK-DAG: %[[A:.+]] = memref.alloc(%[[ARG0]], %[[ARG2]]) : memref<?x?xf32>
24 // CHECK-DAG: %[[B:.+]] = memref.alloc(%[[ARG2]], %[[ARG1]]) : memref<?x?xf32>
31 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
32 // CHECK-DAG: %[[A:.+]] = memref.alloc(%[[ARG0]], %[[ARG2]]) : memref<?x?xf32>
33 // CHECK-DAG: %[[B:.+]] = memref.alloc(%[[ARG2]], %[[ARG1]]) : memref<?x?xf32>
/llvm-project-15.0.7/mlir/test/Conversion/OpenMPToLLVM/
H A Dconvert-to-llvmir.mlir10 // CHECK-NEXT: ^[[BB0:.*]](%[[ARG1:.*]]: i64, %[[ARG2:.*]]: i64):
12 // CHECK-NEXT: llvm.call @foo(%[[ARG1]], %[[ARG2]]) : (i64, i64) -> ()
25 // CHECK-NEXT: ^[[BB0:.*]](%[[ARG1:.*]]: i64, %[[ARG2:.*]]: i64):
28 // CHECK-DAG: %[[CAST_ARG2:.*]] = builtin.unrealized_conversion_cast %[[ARG2]] : i64 to index
46 // CHECK-NEXT: ^[[BB1]](%[[ARG1:[0-9]+]]: i64, %[[ARG2:[0-9]+]]: i64):{{.*}}
48 // CHECK-NEXT: %[[CMP:[0-9]+]] = llvm.icmp "slt" %[[ARG1]], %[[ARG2]] : i64
70 // CHECK: (%[[ARG0:.*]]: i64, %[[ARG1:.*]]: i64, %[[ARG2:.*]]: i64, %[[ARG3:.*]]: i64, %[[ARG4:.*]]…
74 …op for (%[[ARG6:.*]], %[[ARG7:.*]]) : i64 = (%[[ARG0]], %[[ARG1]]) to (%[[ARG2]], %[[ARG3]]) step …
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Dloop-tiling-parametric.mlir18 // CHECK: func @loop_tiling_3d([[ARG0:%arg[0-9]+]]: index, [[ARG1:%arg[0-9]+]]: index, [[ARG2:%arg[…
21 // CHECK-NEXT: affine.for [[ARG5:%arg[0-9]+]] = 0 to [[UBO2]](){{.*}}[[ARG2]]
24 …ine.for %[[K:.*]] = [[LBI]]{{.*}}[[ARG5]]{{.*}}[[ARG2]]{{.*}} to min [[UBI2]]{{.*}}[[ARG5]]{{.*}}[…
50 // CHECK-NEXT: affine.for [[ARG5:%arg[0-9]+]] = 0 to [[UBO2]](){{.*}}[[ARG2]]{{.*}} step 2
53 …ine.for %[[K:.*]] = [[LBI]]{{.*}}[[ARG5]]{{.*}}[[ARG2]]{{.*}} to min [[UBI2]]{{.*}}[[ARG5]]{{.*}}[…
118 // CHECK-NEXT: affine.for [[ARG5:%arg[0-9+]]] = 8 to [[UBO1]]{{.*}}[[ARG2]]{{.*}} step 4
121 … affine.for %[[K:.*]] = [[LBI0]]([[ARG5]]){{.*}}[[ARG2]]{{.*}} to min [[UBI2]]([[ARG5]]){{.*}}[[A…
146 // CHECK-NEXT: affine.for [[ARG5:%arg[0-9]+]] = 0 to [[UBO1]](){{.*}}[[ARG2]]{{.*}}
149 …ine.for %[[K:.*]] = [[LBI]]{{.*}}[[ARG5]]{{.*}}[[ARG2]]{{.*}} to min [[UBI1]]{{.*}}[[ARG5]]{{.*}}[…
179 // CHECK: affine.for [[ARG2:%arg[0-9]+]] = 0 to [[UBO0]](){{.*}}[[ARG0]]{{.*}}
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/MemRef/
H A Dfold-subview-ops.mlir13 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
17 // CHECK-DAG: %[[I2:.+]] = affine.apply #[[MAP1]](%[[ARG4]])[%[[ARG2]]]
32 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
54 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
73 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
94 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
115 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
140 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
183 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]: index
212 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]: index
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dtile-conv.mlir16 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]*]]: memref<?x?xf32>
23 // CHECK-DAG: %[[T2:.*]] = memref.dim %[[ARG2]], %[[C0]]
24 // CHECK-DAG: %[[T3:.*]] = memref.dim %[[ARG2]], %[[C1]]
32 // CHECK: %[[SV2:.*]] = memref.subview %[[ARG2]][%[[ARG3]], %[[ARG4]]] [%[[T6]], %[[T7]…
H A Dtile-and-distribute.mlir14 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]*]]: memref<?x?xf32>
24 // CHECK: %[[SV3:.*]] = memref.subview %[[ARG2]][%[[OFFSETY_2]], %[[OFFSETX]]]
40 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]*]]: memref<?x?xf32>
56 // CHECK: %[[SV3:.*]] = memref.subview %[[ARG2]][%[[OFFSETY_2]], %[[OFFSETX_2]]]
72 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]*]]: memref<?x?xf32>
85 // CHECK: %[[SV3:.*]] = memref.subview %[[ARG2]][%[[ARG3]], %[[ARG4]]]
101 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]*]]: memref<?x?xf32>
130 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]*]]: memref<?x?xf32>
145 // CHECK: %[[SV3:.*]] = memref.subview %[[ARG2]][%[[OFFSETY_2]], %[[ARG3]]]
161 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]*]]: memref<?x?xf32>
[all …]
H A Dpad_fusion.mlir29 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]: index
39 // CHECK-DAG: %[[TARGET_D1:.+]] = affine.apply #[[MAP]]()[%[[ARG2]], %[[ARG4]], %[[SOURCE_D1]]]
45 // CHECK-SAME: [%[[ARG1]], %[[ARG2]]] [%[[SIZE_D0]], %[[SIZE_D1]]] [1, 1]
49 // CHECK-SAME: [%[[ARG1]], %[[ARG2]]] [%[[SIZE_D0]], %[[SIZE_D1]]] [1, 1]
77 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]: index
83 // CHECK-DAG: %[[TARGET_D1:.+]] = affine.apply #[[MAP]]()[%[[ARG1]], %[[ARG2]], %[[SOURCE_D1]]]
H A Dtransform-op-decompose.mlir6 // CHECK-SAME: %[[ARG2:.+]]: tensor<?x1x?x?xf32>
10 // CHECK: %[[SLICE2:.+]] = tensor.extract_slice %[[ARG2]]
12 // CHECK: %[[RES:.+]] = tensor.insert_slice %[[SLICERES]] into %[[ARG2]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Darguments-varargs.ll119 ; ALL-DAG: sh [[ARG2]], 4([[GV]])
234 ; ALL-DAG: sw [[ARG2]], 8([[GV]])
349 ; O32-DAG: sw [[ARG2]], 16([[GV]])
353 ; O32-DAG: sw [[ARG2]], 20([[GV]])
356 ; NEW-DAG: sd [[ARG2]], 16([[GV]])
471 ; ALL-DAG: sh [[ARG2]], 4([[GV]])
586 ; ALL-DAG: sw [[ARG2]], 8([[GV]])
701 ; O32-DAG: sw [[ARG2]], 16([[GV]])
705 ; O32-DAG: sw [[ARG2]], 20([[GV]])
822 ; ALL-DAG: sh [[ARG2]], 4([[GV]])
[all …]
/llvm-project-15.0.7/flang/test/Fir/
H A Dtarget-rewrite-boxchar.fir9 ….ref<!fir.char<1,?>>, [[ARG1:%[0-9A-Za-z]+]]: !fir.ref<!fir.char<1,?>>, [[ARG2:%[0-9A-Za-z]+]]: i3…
11 ….ref<!fir.char<1,?>>, [[ARG1:%[0-9A-Za-z]+]]: !fir.ref<!fir.char<1,?>>, [[ARG2:%[0-9A-Za-z]+]]: i6…
14 …// INT32-DAG: [[B1:%[0-9]+]] = fir.emboxchar [[ARG0]], [[ARG2]] : (!fir.ref<!fir.char<1,?>>, i32) …
18 …// INT64-DAG: [[B1:%[0-9]+]] = fir.emboxchar [[ARG0]], [[ARG2]] : (!fir.ref<!fir.char<1,?>>, i64) …
30 …+]]: !fir.ref<!fir.char<1,?>> {llvm.sret}, [[ARG1:%[0-9A-Za-z]+]]: i32, [[ARG2:%[0-9A-Za-z]+]]: !f…
32 …+]]: !fir.ref<!fir.char<1,?>> {llvm.sret}, [[ARG1:%[0-9A-Za-z]+]]: i64, [[ARG2:%[0-9A-Za-z]+]]: !f…
35 …// INT32-DAG: [[B1:%[0-9]+]] = fir.emboxchar [[ARG2]], [[ARG3]] : (!fir.ref<!fir.char<1,?>>, i32) …
39 …// INT64-DAG: [[B1:%[0-9]+]] = fir.emboxchar [[ARG2]], [[ARG3]] : (!fir.ref<!fir.char<1,?>>, i64) …
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dmetadata-simplify.ll10 ; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
35 ; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
61 ; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
86 ; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
111 ; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
136 ; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/IROutliner/
H A Doutlining-compatible-and-attribute-transfer.ll106 …id @outlined_ir_func_0(float* [[ARG0:%.*]], float* [[ARG1:%.*]], float* [[ARG2:%.*]]) [[ATTR1:#[0-…
110 ; CHECK-NEXT: store float 4.000000e+00, float* [[ARG2]], align 4
113 ; CHECK-NEXT: [[CL:%.*]] = load float, float* [[ARG2]], align 4
115 ; CHECK: define internal void @outlined_ir_func_1(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2…
119 ; CHECK-NEXT: store i32 4, i32* [[ARG2]], align 4
122 ; CHECK-NEXT: [[CL:%.*]] = load i32, i32* [[ARG2]], align 4
H A Doutlining-commutative.ll220 ; CHECK: define internal void @outlined_ir_func_0(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2…
224 ; CHECK-NEXT: store i32 4, i32* [[ARG2]], align 4
227 ; CHECK-NEXT: [[CL:%.*]] = load i32, i32* [[ARG2]], align 4
232 ; CHECK: define internal void @outlined_ir_func_1(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2…
236 ; CHECK-NEXT: store i32 4, i32* [[ARG2]], align 4
239 ; CHECK-NEXT: [[CL:%.*]] = load i32, i32* [[ARG2]], align 4
244 ; CHECK: define internal void @outlined_ir_func_2(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2…
248 ; CHECK-NEXT: store i32 4, i32* [[ARG2]], align 4
251 ; CHECK-NEXT: [[CL:%.*]] = load i32, i32* [[ARG2]], align 4
H A Doutlining-constants-vs-registers.ll72 ; CHECK: define internal void @outlined_ir_func_0(i32 [[ARG0:%.*]], i32 [[ARG1:%.*]], i32 [[ARG2:%.…
75 ; CHECK-NEXT: add i32 [[ARG2]], [[ARG3]]
78 ; CHECK: define internal void @outlined_ir_func_1(i32 [[ARG0:%.*]], i32* [[ARG1:%.*]], i32 [[ARG2:%…
81 ; CHECK-NEXT: store i32 [[ARG2]], i32* [[ARG3]]
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dnofree.ll372 ; ATTRIBUTOR-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]])
373 ; ATTRIBUTOR-NEXT: call void @unknown(i8* [[ARG1]], i8* [[ARG2]], i8* [[ARG3]], i8* [[ARG4]])
378 ; CHECK-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]]) {
379 ; CHECK-NEXT: call void @unknown(i8* [[ARG1]], i8* [[ARG2]], i8* [[ARG3]], i8* [[ARG4]])
389 ; ATTRIBUTOR-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]])
392 ; ATTRIBUTOR-NEXT: call void @use_i8_ptr(i8* noalias readnone [[ARG2]])
397 ; ATTRIBUTOR-NEXT: call void @use_i8_ptr_ret(i8* noalias readnone [[ARG2]])
404 ; CHECK-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]]) {
405 ; CHECK-NEXT: call void @unknown(i8* [[ARG1]], i8* [[ARG2]], i8* [[ARG3]], i8* [[ARG4]])
407 ; CHECK-NEXT: call void @use_i8_ptr(i8* noalias nocapture readnone [[ARG2]]) #[[ATTR0]]
[all …]
/llvm-project-15.0.7/llvm/test/Bitcode/
H A Dupgrade-ptr-annotation.ll10 ;CHECK: @f1(i8* [[ARG0:%.*]], i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i32 [[ARG3:%.*]])
12 ;CHECK: call i8* @llvm.ptr.annotation.p0i8(i8* [[ARG0]], i8* [[ARG1]], i8* [[ARG2]], i32 [[ARG3]],…
17 ;CHECK: call i16* @llvm.ptr.annotation.p0i16(i16* [[ARG0_P16]], i8* [[ARG1]], i8* [[ARG2]], i32 [[…
22 ;CHECK: call i256* @llvm.ptr.annotation.p0i256(i256* [[ARG0_P256]], i8* [[ARG1]], i8* [[ARG2]], i3…
H A Dupgrade-var-annotation.ll7 ;CHECK: @f(i8* [[ARG0:%.*]], i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i32 [[ARG3:%.*]])
9 ;CHECK: call void @llvm.var.annotation(i8* [[ARG0]], i8* [[ARG1]], i8* [[ARG2]], i32 [[ARG3]], i8*…
/llvm-project-15.0.7/mlir/test/Dialect/Tensor/
H A Dresolve-shaped-type-result-dims.mlir46 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
48 // CHECK: return %[[ARG1]], %[[ARG2]], %[[ARG3]]
125 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
126 // CHECK: return %[[ARG1]], %[[ARG2]]
143 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
144 // CHECK: return %[[ARG1]], %[[ARG2]]
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-reduce-to-contract.mlir7 // CHECK-SAME: (%[[ARG0:.*]]: vector<8x32x16xf32>, %[[ARG1:.*]]: vector<8x32x16xf32>, %[[ARG2:.*]]…
10 // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]] : vector<8x32x16xf32>, vector<8x32x16xf32> into v…
28 // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]] : vector<8x32x16xi32>, vector<8x32x16xi32> into v…
103 // CHECK-SAME: (%[[ARG0:.+]]: vector<8x4xi32>, %[[ARG1:.+]]: vector<8x4xi32>, %[[ARG2:.+]]: vector…
107 // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]] : vector<8x4xi32>, vector<8x4xi32> into vector<8x8x…
135 // CHECK-SAME: (%[[ARG0:.+]]: vector<8x4xi32>, %[[ARG1:.+]]: vector<8x4xi32>, %[[ARG2:.+]]: vector…
167 // CHECK-SAME: (%[[ARG0:.+]]: vector<8xi32>, %[[ARG1:.+]]: vector<8xi32>, %[[ARG2:.+]]: vector<8x8…
199 // CHECK-SAME: (%[[ARG0:.+]]: vector<1x2xi32>, %[[ARG1:.+]]: vector<2xi32>, %[[ARG2:.+]]: vector<1…
204 // CHECK-SAME: %[[ARG0]], %[[BROADCAST1]], %[[ARG2]] : vector<1x2xi32>, vector<1x1x2xi32> into vec…
230 // CHECK-SAME: (%[[ARG0:.+]]: vector<1xf32>, %[[ARG1:.+]]: vector<1xf32>, %[[ARG2:.+]]: vector<1xf…
[all …]

1234567