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/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dto_addr_builtin.cl18 //CHECK: %[[ARG:.*]] = addrspacecast i32 addrspace(1)* %{{.*}} to i8 addrspace(4)*
23 //CHECK: %[[ARG:.*]] = addrspacecast i32 addrspace(3)* %{{.*}} to i8 addrspace(4)*
28 //CHECK: %[[ARG:.*]] = addrspacecast i32* %{{.*}} to i8 addrspace(4)*
33 //CHECK: %[[ARG:.*]] = bitcast i32 addrspace(4)* %{{.*}} to i8 addrspace(4)*
38 //CHECK: %[[ARG:.*]] = addrspacecast i32 addrspace(1)* %{{.*}} to i8 addrspace(4)*
43 //CHECK: %[[ARG:.*]] = addrspacecast i32 addrspace(3)* %{{.*}} to i8 addrspace(4)*
48 //CHECK: %[[ARG:.*]] = addrspacecast i32* %{{.*}} to i8 addrspace(4)*
53 //CHECK: %[[ARG:.*]] = bitcast i32 addrspace(4)* %{{.*}} to i8 addrspace(4)*
68 //CHECK: %[[ARG:.*]] = addrspacecast i32* %{{.*}} to i8 addrspace(4)*
73 //CHECK: %[[ARG:.*]] = bitcast i32 addrspace(4)* %{{.*}} to i8 addrspace(4)*
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dpointer-collision-non-determinism.ll38 ; CHECK-NEXT: [[TMP5:%.*]] = fadd fast float [[TMP4]], [[ARG]]
39 ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP5]], [[ARG]]
40 ; CHECK-NEXT: [[TMP7:%.*]] = fadd fast float [[TMP6]], [[ARG]]
41 ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP7]], [[ARG]]
42 ; CHECK-NEXT: [[TMP9:%.*]] = fadd fast float [[TMP8]], [[ARG]]
43 ; CHECK-NEXT: [[TMP10:%.*]] = fmul fast float [[TMP9]], [[ARG]]
44 ; CHECK-NEXT: [[TMP11:%.*]] = fadd fast float [[TMP10]], [[ARG]]
45 ; CHECK-NEXT: [[TMP12:%.*]] = fmul fast float [[TMP11]], [[ARG]]
46 ; CHECK-NEXT: [[TMP13:%.*]] = fadd fast float [[TMP12]], [[ARG]]
57 ; CHECK-NEXT: [[REASS_MUL166:%.*]] = fmul fast float [[ARG]], [[ARG]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Daddsub-constant-folding.ll11 ; CHECK-NEXT: [[T1:%.*]] = add i32 [[ARG:%.*]], 10
21 ; CHECK-NEXT: [[T0:%.*]] = add i32 [[ARG:%.*]], 8
23 ; CHECK-NEXT: [[T1:%.*]] = add i32 [[ARG]], 10
69 ; CHECK-NEXT: [[T1:%.*]] = add i32 [[ARG:%.*]], 6
79 ; CHECK-NEXT: [[T0:%.*]] = add i32 [[ARG:%.*]], 8
81 ; CHECK-NEXT: [[T1:%.*]] = add i32 [[ARG]], 6
139 ; CHECK-NEXT: [[T1:%.*]] = sub i32 -6, [[ARG]]
197 ; CHECK-NEXT: [[T1:%.*]] = add i32 [[ARG]], -6
313 ; CHECK-NEXT: [[T1:%.*]] = sub i32 10, [[ARG]]
371 ; CHECK-NEXT: [[T1:%.*]] = sub i32 10, [[ARG]]
[all …]
H A Dsigned-truncation-check.ll314 ; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
328 ; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
342 ; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
356 ; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
480 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 128
501 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 128
524 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
549 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
574 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[ARG]], 24
603 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[ARG]], 24
[all …]
H A Dselect-of-bittest.ll10 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 3
101 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 3
308 ; CHECK-NEXT: [[T:%.*]] = and i32 [[ARG:%.*]], 1
486 ; CHECK-NEXT: [[T3:%.*]] = and i32 [[ARG]], 1
543 ; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[ARG]], 2
560 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[ARG]], 1
577 ; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[ARG]], 2
594 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[ARG]], 2
611 ; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[ARG]], 2
628 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[ARG]], 1
[all …]
H A Dselect-cmp-br.ll19 ; CHECK-NEXT: [[TMP71:%.*]] = icmp eq %C* [[ARG]], null
25 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
32 ; CHECK-NEXT: [[TMP11:%.*]] = tail call i64 [[TMP4]](%C* [[ARG]])
69 ; CHECK-NEXT: [[TMP71:%.*]] = icmp eq %C* [[ARG]], null
82 ; CHECK-NEXT: [[TMP11:%.*]] = tail call i64 [[TMP4]](%C* [[ARG]])
119 ; CHECK-NEXT: [[TMP7_NOT1:%.*]] = icmp eq %C* [[ARG]], null
132 ; CHECK-NEXT: [[TMP11:%.*]] = tail call i64 [[TMP4]](%C* [[ARG]])
169 ; CHECK-NEXT: [[TMP7_NOT1:%.*]] = icmp eq %C* [[ARG]], null
182 ; CHECK-NEXT: [[TMP11:%.*]] = tail call i64 [[TMP4]](%C* [[ARG]])
214 ; CHECK-NEXT: [[TMP2_NOT1:%.*]] = icmp eq %C* [[ARG:%.*]], null
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dround-intrinsics.ll6 ; CHECK-NEXT: [[CVT:%.*]] = sitofp i32 [[ARG:%.*]] to float
16 ; CHECK-NEXT: [[CVT:%.*]] = uitofp i32 [[ARG:%.*]] to float
26 ; CHECK-NEXT: [[CVT:%.*]] = sitofp i32 [[ARG:%.*]] to float
36 ; CHECK-NEXT: [[CVT:%.*]] = uitofp i32 [[ARG:%.*]] to float
46 ; CHECK-NEXT: [[CVT:%.*]] = sitofp i32 [[ARG:%.*]] to float
56 ; CHECK-NEXT: [[CVT:%.*]] = uitofp i32 [[ARG:%.*]] to float
66 ; CHECK-NEXT: [[CVT:%.*]] = sitofp i32 [[ARG:%.*]] to float
76 ; CHECK-NEXT: [[CVT:%.*]] = uitofp i32 [[ARG:%.*]] to float
86 ; CHECK-NEXT: [[CVT:%.*]] = uitofp i32 [[ARG:%.*]] to float
96 ; CHECK-NEXT: [[CVT:%.*]] = sitofp i32 [[ARG:%.*]] to float
[all …]
/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/
H A Dpre-process.ll.expected17 ; CHECK-AS200-SAME: (i8 addrspace(200)* [[ARG:%.*]]) addrspace(200) #[[ATTR0:[0-9]+]] {
19 ; CHECK-AS200-NEXT: ret i8 addrspace(200)* [[ARG]]
22 ; CHECK-AS0-SAME: (i8* [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
24 ; CHECK-AS0-NEXT: ret i8* [[ARG]]
27 ; CHECK-AS1-SAME: (i8 addrspace(1)* [[ARG:%.*]]) addrspace(1) #[[ATTR0:[0-9]+]] {
29 ; CHECK-AS1-NEXT: ret i8 addrspace(1)* [[ARG]]
32 ; CHECK-AS200-NOOP-PRE-PROCESS-SAME: (i8 addrspace(200)* [[ARG:%.*]]) addrspace(200) #[[ATTR0:[0-9]…
34 ; CHECK-AS200-NOOP-PRE-PROCESS-NEXT: ret i8 addrspace(200)* [[ARG]]
/llvm-project-15.0.7/mlir/test/Conversion/FuncToSPIRV/
H A Dfunc-ops-to-spirv.mlir18 // CHECK-SAME: (%[[ARG:.+]]: f32)
20 // CHECK: spv.ReturnValue %[[ARG]] : f32
32 // CHECK-SAME: (%[[ARG:.+]]: i32)
34 // CHECK: spv.ReturnValue %[[ARG]] : i32
39 // CHECK-SAME: (%[[ARG:.+]]: i32)
43 // CHECK: {{%.*}} = spv.FunctionCall @return_one_index(%[[ARG]]) : (i32) -> i32
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dunsigned-multiply-overflow-check.ll23 ; SIMPLIFYCFG-NEXT: [[T0:%.*]] = icmp eq i64 [[ARG:%.*]], 0
26 ; SIMPLIFYCFG-NEXT: [[T3:%.*]] = udiv i64 -1, [[ARG]]
35 ; INSTCOMBINEONLY-NEXT: [[T0:%.*]] = icmp eq i64 [[ARG:%.*]], 0
38 ; INSTCOMBINEONLY-NEXT: [[UMUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[ARG]]…
47 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT: [[T0:%.*]] = icmp eq i64 [[ARG:%.*]], 0
48 …EXT: [[UMUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[ARG]], i64 [[ARG1:%.*]])
79 ; SIMPLIFYCFG-NEXT: [[T0:%.*]] = icmp eq i64 [[ARG:%.*]], 0
82 ; SIMPLIFYCFG-NEXT: [[T3:%.*]] = udiv i64 -1, [[ARG]]
92 ; INSTCOMBINEONLY-NEXT: [[T0:%.*]] = icmp eq i64 [[ARG:%.*]], 0
95 ; INSTCOMBINEONLY-NEXT: [[UMUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[ARG]]…
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Util/
H A Dcall-promotion-utils-ptrcast.ll30 ; CHECK: [[ARG:%[0-9]+]] = bitcast i64 1 to double
31 ; CHECK-NEXT: [[RET:%[0-9]+]] = call i8* @func4(double [[ARG]])
37 ; CHECK: [[ARG:%[0-9]+]] = inttoptr i64 1 to i8*
38 ; CHECK-NEXT: [[RET:%[0-9]+]] = call i8* @func3(i8* [[ARG]])
41 ; CHECK: [[ARG:%[0-9]+]] = inttoptr i64 1 to i8*
42 ; CHECK-NEXT: call i64 @func1(i8* [[ARG]])
/llvm-project-15.0.7/llvm/test/tools/llvm-objcopy/
H A Dtool-help-message.test5 # RUN: not llvm-objcopy -abcabc 2>&1 | FileCheck --check-prefix=UNKNOWN-ARG-SHORT %s
6 # RUN: not llvm-objcopy --abcabc 2>&1 | FileCheck --check-prefix=UNKNOWN-ARG-LONG %s
13 # RUN: not llvm-strip -abcabc 2>&1 | FileCheck --check-prefix=UNKNOWN-ARG-SHORT %s
14 # RUN: not llvm-strip --abcabc 2>&1 | FileCheck --check-prefix=UNKNOWN-ARG-LONG %s
20 # RUN: not llvm-install-name-tool -abcabc 2>&1 | FileCheck --check-prefix=UNKNOWN-ARG-LONG %s
21 # RUN: not llvm-install-name-tool --abcabc 2>&1 | FileCheck --check-prefix=UNKNOWN-ARG-LONG %s
28 # RUN: not llvm-bitcode-strip -abcabc 2>&1 | FileCheck --check-prefix=UNKNOWN-ARG-LONG %s
29 # RUN: not llvm-bitcode-strip --abcabc 2>&1 | FileCheck --check-prefix=UNKNOWN-ARG-LONG %s
44 # UNKNOWN-ARG-SHORT: unknown argument '-a'
45 # UNKNOWN-ARG-LONG: unknown argument '{{-+}}abcabc'
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dvalue-simplify-assume.ll167 ; IS__TUNIT____-NEXT: ret i1 [[ARG]]
175 ; IS__CGSCC____-NEXT: ret i1 [[ARG]]
278 ; IS__TUNIT____-NEXT: ret i1 [[ARG]]
292 ; IS__CGSCC____-NEXT: ret i1 [[ARG]]
813 ; CHECK-SAME: (i1 [[ARG:%.*]]) {
836 ; IS__TUNIT____-NEXT: ret i1 [[ARG]]
844 ; IS__CGSCC____-NEXT: ret i1 [[ARG]]
855 ; CHECK-SAME: (i1 [[ARG:%.*]]) {
877 ; IS__TUNIT____-SAME: (i1 [[ARG:%.*]]) {
942 ; IS__TUNIT____-NEXT: ret i1 [[ARG]]
[all …]
H A Dchain.ll11 ; CHECK_1-SAME: (i32* dereferenceable_or_null(8) [[ARG:%.*]]) {
13 ; CHECK_1-NEXT: [[BC1:%.*]] = bitcast i32* [[ARG]] to i8*
15 ; CHECK_1-NEXT: [[LD:%.*]] = load i32, i32* [[ARG]], align 4
19 ; CHECK_5-SAME: (i32* nonnull dereferenceable(8) [[ARG:%.*]]) {
21 ; CHECK_5-NEXT: [[BC1:%.*]] = bitcast i32* [[ARG]] to i8*
23 ; CHECK_5-NEXT: [[LD:%.*]] = load i32, i32* [[ARG]], align 4
/llvm-project-15.0.7/llvm/test/Transforms/ArgumentPromotion/
H A Dstore-after-load.ll6 ; CHECK-SAME: (i32* [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
8 ; CHECK-NEXT: [[TEMP:%.*]] = load i32, i32* [[ARG]], align 4
10 ; CHECK-NEXT: store i32 [[SUM]], i32* [[ARG]], align 4
22 ; CHECK-SAME: (i32* [[ARG:%.*]]) #[[ATTR0]] {
24 ; CHECK-NEXT: call void @callee(i32* [[ARG]]) #[[ATTR0]]
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/ArgumentPromotion/
H A Dalloca-as.ll13 ; IS________OPM-SAME: (i32 [[ARG:%.*]]) {
16 ; IS________OPM-NEXT: store i32 [[ARG]], i32* [[STACK]], align 4
21 ; IS__TUNIT_NPM-SAME: (i32 [[ARG:%.*]]) {
24 ; IS__TUNIT_NPM-NEXT: store i32 [[ARG]], i32* [[STACK]], align 4
30 ; IS__CGSCC_NPM-SAME: (i32 [[ARG:%.*]]) {
33 ; IS__CGSCC_NPM-NEXT: store i32 [[ARG]], i32* [[STACK]], align 4
34 ; IS__CGSCC_NPM-NEXT: [[CALL:%.*]] = call i32 @foo(i32 [[ARG]])
46 …: (i32* noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[ARG:%.*]]) {
48 ; IS________OPM-NEXT: [[L:%.*]] = load i32, i32* [[ARG]], align 4
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/
H A Dmin-legal-vector-width.ll19 ; IS________OPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
29 ; IS________NPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
50 ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
64 ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
77 ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
91 ; IS__CGSCC_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
113 ; IS________OPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
123 ; IS________NPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
144 ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
158 ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
[all …]
H A Dattributes.ll17 ; IS________OPM-NEXT: store <4 x i64> [[TMP]], <4 x i64>* [[ARG]], align 32
25 ; IS________NPM-NEXT: store <4 x i64> [[TMP]], <4 x i64>* [[ARG]], align 32
45 ; IS__TUNIT_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
58 ; IS__TUNIT_NPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
71 ; IS__CGSCC_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
84 ; IS__CGSCC_NPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
104 ; IS________OPM-NEXT: store <4 x i64> [[TMP]], <4 x i64>* [[ARG]], align 32
114 ; IS________NPM-NEXT: store <4 x i64> [[TMP]], <4 x i64>* [[ARG]], align 32
134 ; IS__TUNIT_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
148 ; IS__TUNIT_NPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/ArgumentPromotion/X86/
H A Dmin-legal-vector-width.ll11 ; CHECK-SAME: (<8 x i64>* [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]])
13 ; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], <8 x i64>* [[ARG]]
24 ; CHECK-SAME: (<8 x i64>* [[ARG:%.*]])
63 ; CHECK-SAME: (<8 x i64>* [[ARG:%.*]])
102 ; CHECK-SAME: (<8 x i64>* [[ARG:%.*]])
141 ; CHECK-SAME: (<8 x i64>* [[ARG:%.*]])
170 ; CHECK-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]]
181 ; CHECK-SAME: (<8 x i64>* [[ARG:%.*]])
220 ; CHECK-SAME: (<8 x i64>* [[ARG:%.*]])
258 ; CHECK-SAME: (<8 x i64>* [[ARG:%.*]])
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/DeadStoreElimination/
H A Dmultiblock-overlap.ll15 ; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds [[STRUCT_HAM:%.*]], %struct.ham* [[ARG:%.*]],…
16 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_HAM]], %struct.ham* [[ARG]], i64 0,…
17 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_HAM]], %struct.ham* [[ARG]], i64 0,…
18 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_HAM]], %struct.ham* [[ARG]], i64 0,…
19 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_HAM]], %struct.ham* [[ARG]], i64 0,…
20 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_HAM]], %struct.ham* [[ARG]], i64 0,…
66 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_HAM]], %struct.ham* [[ARG]], i64 0,…
67 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_HAM]], %struct.ham* [[ARG]], i64 0,…
68 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_HAM]], %struct.ham* [[ARG]], i64 0,…
124 ; CHECK-NEXT: [[CAST_I32:%.*]] = bitcast [4 x i8]* [[ARG:%.*]] to i32*
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/GVNHoist/
H A Dopaque-diff-type.ll12 ; CHECK-NEXT: [[T:%.*]] = load i16, ptr [[ARG:%.*]], align 4
15 ; CHECK-NEXT: [[T3:%.*]] = load i32, ptr [[ARG]], align 8
35 ; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[ARG:%.*]], align 4
38 ; CHECK-NEXT: [[T3:%.*]] = load float, ptr [[ARG]], align 8
58 ; CHECK-NEXT: [[T:%.*]] = load i64, ptr [[ARG:%.*]], align 4
61 ; CHECK-NEXT: [[T3:%.*]] = load ptr, ptr [[ARG]], align 8
81 ; CHECK-NEXT: [[T:%.*]] = load ptr addrspace(4), ptr [[ARG:%.*]], align 4
84 ; CHECK-NEXT: [[T3:%.*]] = load ptr addrspace(2), ptr [[ARG]], align 8
102 ; CHECK-NEXT: [[T3:%.*]] = load ptr, ptr [[ARG:%.*]], align 4
/llvm-project-15.0.7/mlir/test/Dialect/Bufferization/
H A Dcanonicalize.mlir121 // CHECK-SAME: %[[ARG:.*]]: memref<?xf32>
122 // CHECK-NEXT: return %[[ARG]]
133 // CHECK-SAME: %[[ARG:.*]]: memref<?xf32>
135 // CHECK-NEXT: return %[[ARG]]
145 // CHECK-SAME: %[[ARG:.*]]: memref<?xf32>
157 // CHECK-SAME: %[[ARG:.*]]: memref<?xf32>
190 // CHECK-SAME: %[[ARG:.*]]: memref<?xf32>
192 // CHECK: memref.dealloc %[[ARG]]
193 // CHECK: memref.dealloc %[[ARG]]
199 // CHECK-SAME: %[[ARG:.*]]: memref<?xf32>
[all …]
/llvm-project-15.0.7/mlir/test/Conversion/BufferizationToMemRef/
H A Dbufferization-to-memref.mlir11 // CHECK-NEXT: memref.copy %[[ARG:.*]], %[[ALLOC]]
12 // CHECK-NEXT: memref.dealloc %[[ARG]]
25 // CHECK-NEXT: %[[DIM:.*]] = memref.dim %[[ARG:.*]], %[[CONST]]
27 // CHECK-NEXT: memref.copy %[[ARG]], %[[ALLOC]]
28 // CHECK-NEXT: memref.dealloc %[[ARG]]
45 // CHECK-SAME: %[[ARG:.*]]: memref<?xf32, #[[$MAP]]>
47 // CHECK: %[[DIM:.*]] = memref.dim %[[ARG]], %[[C0]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dcombine-add-zext-xor.ll8 ; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
9 ; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
39 ; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
40 ; CHECK: v_sub_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
71 ; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
72 ; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
104 ; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
105 ; CHECK: v_sub_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
137 ; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
138 ; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
[all …]
/llvm-project-15.0.7/mlir/test/Transforms/
H A Dscf-replace-with-new-yields.mlir12 // CHECK-SAME: %[[ARG:[a-zA-Z0-9]+]]: f32
14 // CHECK-SAME: iter_args(%[[INIT1:.+]] = %[[ARG]], %[[INIT2:.+]] = %[[ARG]]
19 // CHECK-SAME: iter_args(%[[INIT:.+]] = %[[ARG]])

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