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Searched refs:AI1 (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrInfo.td1733 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1747 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1764 def rsi : AI1<opcod, (outs),
1781 def rsr : AI1<opcod, (outs),
2412 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
3641 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3667 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
4897 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4913 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4930 def CMNzrsi : AI1<0b1011, (outs),
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H A DARMInstrFormats.td744 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16x2-instructions.ll1286 ; CHECK-DAG: and.b16 [[AI1:%rs[0-9]+]], [[AS1]], 32767;
1294 ; CHECK-DAG: or.b16 [[RS1:%rs[0-9]+]], [[AI1]], [[BZ1]];
1315 ; CHECK-DAG: and.b16 [[AI1:%rs[0-9]+]], [[AS1]], 32767;
1323 ; CHECK-DAG: or.b16 [[RS1:%rs[0-9]+]], [[AI1]], [[BZ1]];
/llvm-project-15.0.7/llvm/lib/Transforms/Coroutines/
H A DCoroFrame.cpp652 auto IsAllocaInferenre = [&](const AllocaInst *AI1, const AllocaInst *AI2) { in addFieldForAllocas() argument
653 return StackLifetimeAnalyzer.getLiveRange(AI1).overlaps( in addFieldForAllocas()