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Searched refs:AH (Results 1 – 25 of 54) sorted by relevance

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/llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/
H A Ddfdiv.S12 #define AH r1 macro
81 EXPBA = combine(BH,AH)
82 SIGN = xor(AH,BH)
85 #undef AH
208 #define AH r1 macro
329 AH = mux(Q_POSITIVE,#0,#-1) define
338 QH ^= lsr(AH,#31)
402 EXPBA = combine(BH,AH)
407 if (P_TMP) AH = or(AH,TMP) // if normal, add back in hidden bit
435 AH = xor(AH,BH) define
[all …]
H A Ddfmul.S11 #define AH r1 macro
113 EXP0 = extractu(AH,#EXPBITS,#HI_MANTBITS)
119 TMP = xor(AH,BH)
133 AH += asl(EXP0,#HI_MANTBITS)
150 p0 = bitsclr(AH,BTMPL)
177 AH += asl(EXP1,#HI_MANTBITS)
178 EXP1 = extractu(AH,#EXPBITS,#HI_MANTBITS)
232 AH = insert(S_ZERO,#EXPBITS,#HI_MANTBITS) define
328 p0 = bitsclr(AH,TMP)
342 AH -= asl(TMP,#HI_MANTBITS)
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H A Ddfaddsub.S12 #define AH r1 macro
79 EXPA = extractu(AH,#EXPBITS,#HI_MANTBITS)
111 A_POS = cmp.gt(AH,#-1)
148 AH += asl(EXPB,#HI_MANTBITS)
174 if (p0.new) AH = xor(AH,BH)
199 TMP = extractu(AH,#EXPBITS,#HI_MANTBITS)
200 AH += asl(EXPB,#HI_MANTBITS)
292 EXPA = extractu(AH,#EXPBITS,#HI_MANTBITS)
315 p0 = cmp.gt(AH,#-1)
336 if (!p0) AH = or(AH,BH)
[all …]
H A Ddffma.S16 #define AH r1 macro
147 TMP = xor(AH,BH)
406 AH = USR define
426 if (!p1.new) AH = or(AH,AL)
431 USR = AH
438 AH += asl(TMP,#HI_MANTBITS)
448 p0 = bitsclr(AH,TMP)
480 BH ^= lsr(AH,#31)
549 p0 = bitsclr(AH,TMP)
560 AH -= asl(TMP,#HI_MANTBITS)
[all …]
H A Ddfsqrt.S14 #define AH r1 macro
81 EXP = extractu(AH,#DF_EXPBITS,#DF_MANTBITS-32)
86 NORMAL = cmp.gt(AH,#-1) // and positive?
99 #undef AH
339 #define AH r1 macro
361 P_TMP = cmp.gt(AH,#-1)
382 AH = insert(EXP,#1,#DF_MANTBITS-32) // insert lsb of exponent define
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
6 %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1]
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
25 %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-add-01.ll6 ; Check the low end of the AH range.
17 ; Check the high end of the aligned AH range.
29 ; Check the next halfword up, which should use AHY instead of AH.
105 ; Check that AH allows an index.
H A Dint-sadd-02.ll8 ; Check the low end of the AH range.
26 ; Check the high end of the aligned AH range.
45 ; Check the next halfword up, which should use AHY instead of AH.
163 ; Check that AH allows an index.
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DBenchmarkResultTest.cpp64 .addReg(X86::AH) in TEST()
70 RegisterValue{X86::AH, APInt(8, "123", 10)}}; in TEST()
H A DRegisterAliasingTest.cpp35 X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX}; in TEST_F()
H A DTargetTest.cpp145 EXPECT_TRUE(State.getRATC().reservedRegisters().test(X86::AH)); in TEST_F()
/llvm-project-15.0.7/bolt/unittests/Core/
H A DMCPlusBuilder.cpp103 uint64_t AliasesAX[] = {X86::RAX, X86::EAX, X86::AX, X86::AL, X86::AH}; in TEST_P()
109 uint64_t AliasesAX[] = {X86::AX, X86::AL, X86::AH}; in TEST_P()
/llvm-project-15.0.7/llvm/test/tools/llvm-exegesis/X86/
H A Danalysis-clustering-algorithms.test48 - 'ROL8ri AH AH i_0x1'
69 - 'AH=0x0'
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2010-02-23-DIV8rDefinesAX.ll4 ; This test produces a DIV8r instruction and uses %AX instead of %AH and %AL.
H A Dcrash-O0.ll8 ; The DIV8 instruction produces results in AH and AL, but we don't want to use
9 ; AH in 64-bit mode. The hack used must not generate copyFromReg nodes for
H A D2010-03-04-Mul8Bug.ll5 ; from the AX register instead of AH/AL. That confuses live interval analysis.
H A Dbmi-x86_64.ll36 ; Make sure we still use the AH subreg trick to extract 15:8
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp183 {codeview::RegisterId::AH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
757 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
758 return X86::AH; in getX86SubSuperRegisterOrZero()
769 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
806 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
842 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
878 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td58 def AH : X86Reg<"ah", 4>;
115 def AX : X86Reg<"ax", 0, [AL,AH]>;
391 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
397 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
399 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
457 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
470 (add AL, CL, DL, AH, CH, DH, BL, BH)> {
471 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
H A DREADME-X86-64.txt44 It's not possible to reference AH, BH, CH, and DH registers in an instruction
45 requiring REX prefix. However, divb and mulb both produce results in AH. If isel
H A DX86InstrArithmetic.td58 // AL,AH = AL*GR8
83 // AL,AH = AL*[mem8]
109 // AL,AH = AL*GR8
127 // AL,AH = AL*[mem8]
283 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
284 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
298 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
299 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
315 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
316 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
[all …]
H A DX86InstructionSelector.cpp1531 {X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S}, // SRem in selectDivRem()
1533 {X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U}, // URem in selectDivRem()
1647 OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) { in selectDivRem()
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16-instructions.ll808 ; CHECK: ld.param.b16 [[AH:%h[0-9]+]], [test_bitcast_halftoi16_param_0];
809 ; CHECK: mov.b16 [[AS:%rs[0-9]+]], [[AH]]
820 ; CHECK: mov.b16 [[AH:%h[0-9]+]], [[AS]]
821 ; CHECK: st.param.b16 [func_retval0+0], [[AH]];
1008 ; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_param_0];
1010 ; CHECK-DAG: mov.b16 [[AS:%rs[0-9]+]], [[AH]];
1024 ; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_f32_param_0];
1026 ; CHECK-DAG: mov.b16 [[A:%rs[0-9]+]], [[AH]];
1043 ; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_f64_param_0];
1045 ; CHECK-DAG: mov.b16 [[A:%rs[0-9]+]], [[AH]];
[all …]
/llvm-project-15.0.7/clang/include/clang/Sema/
H A DLookup.h275 void setAllowHidden(bool AH) { in setAllowHidden() argument
276 AllowHidden = AH; in setAllowHidden()
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h80 ENTRY(AH) \

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