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Searched refs:ADR (Results 1 – 25 of 51) sorted by relevance

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/llvm-project-15.0.7/clang/test/CodeGenOpenCLCXX/
H A Daddress-space-deduction.clcpp6 #define ADR(x) x
9 #define ADR(x) &x
16 int PTR glob_p = ADR(glob);
32 int PTR loc_p = ADR(loc);
34 const __private int PTR loc_p_const = ADR(loc);
38 static int PTR loc_st_p = ADR(loc_st);
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-gv-cmodel-tiny.mir33 ; CHECK: [[ADR:%[0-9]+]]:gpr64 = ADR @foo1
34 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY [[ADR]]
35 ; CHECK: [[ADR1:%[0-9]+]]:gpr64 = ADR @foo2
H A Dselect-gv-with-offset.mir33 ; TINY: %g:gpr64 = ADR @g + 1
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/AArch64/
H A Dmir-canon-constant-pool-hash.mir17 ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR
18 ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Dno-iv-rewrite.ll22 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDVARS_IV]]
23 ; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ADR]], align 4
76 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDVARS_IV]]
77 ; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ADR]], align 4
131 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[PTRIV]], i64 [[OFS]]
132 ; CHECK-NEXT: store i32 3, i32* [[ADR]], align 4
173 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr [[STRUCTI:%.*]], %structI* [[P]], i32 0, i32 0
174 ; CHECK-NEXT: store i32 3, i32* [[ADR]], align 4
216 ; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ADR]], align 4
304 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr i64, i64* [[BASE:%.*]], i64 [[INDVARS_IV]]
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dmacho-adrp-missing-reloc.s3 ; CHECK: error: ADR/ADRP relocations must be GOT relative
/llvm-project-15.0.7/lld/test/ELF/
H A Daarch64-adrp-ldr-got.s33 # RUN: llvm-objdump --no-show-raw-insn -d %t/a | FileCheck --check-prefix=ADR %s
36 # ADR: nop
37 # ADR-NEXT: adr x1
/llvm-project-15.0.7/bolt/test/AArch64/
H A Dskip-got-rel.test2 // processed normally with BOLT and the ADR instruction address is recognized
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64ExternalSymbolizer.cpp110 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
119 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
/llvm-project-15.0.7/bolt/test/runtime/AArch64/
H A Dadrrelaxationpass.s1 # The second and third ADR instructions are non-local to functions
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Djump-table-islands-split.ll8 ; eliminate the entry calculation (ADD) and use the ADR as the base.
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-adr.ll7 ; ADR
H A Djump-table-compress.mir82 …; First destination is (2^20 - 4) after reference. Just reachable by ADR so can use compressed tab…
96 ; First destination is 2^20 before reference. Just within reach of ADR.
106 ; First destination is 2^20 before reference. Just within reach of ADR.
H A Daarch64-interleaved-ld-combine.ll73 ; AS-DAG: add [[ADR:x[0-9]+]], x0, [[AND]]
74 …-DAG: ld4 { v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, [[[ADR]]]
135 ; AS-DAG: add [[ADR:x[0-9]+]], [[ADD]], [[AND]]
136 …-DAG: ld4 { v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, [[[ADR]]]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedPredExynos.td122 [ADR, ADRP,
H A DAArch64MacroFusion.cpp228 case AArch64::ADR: in isAddressLdStPair()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopRerollPass.cpp902 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(DRS.BaseInst)); in validateRootSet() local
903 if (!ADR) in validateRootSet()
908 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(DRS.Roots[0]), ADR); in validateRootSet()
912 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) in validateRootSet()
/llvm-project-15.0.7/bolt/lib/Target/AArch64/
H A DAArch64MCPlusBuilder.cpp63 return Inst.getOpcode() == AArch64::ADR; in isADR()
240 if (Inst.getOpcode() == AArch64::ADR) { in evaluateADR()
571 assert(DefBaseAddr->getOpcode() == AArch64::ADR && in analyzeIndirectBranchFragment()
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dthumb1.txt55 # ADR
/llvm-project-15.0.7/lld/test/MachO/
H A Dloh-adrp-ldr-got-ldr.s148 ### Transformation to ADR+LDR
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/
H A Dscevunroll.ll15 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[BASE:%.*]], i64 9
16 ; CHECK-NEXT: [[TMP:%.*]] = load i32, i32* [[ADR]], align 8
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td134 def ADR : BinaryRR<"adr", 0x2A, null_frag, FP64, FP64>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp244 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR in getAdrLabelOpValue()
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dbasic-thumb-instructions.s86 @ ADR
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp1379 : ARM::ADR)) in emitInstruction()
1395 : ARM::ADR)) in emitInstruction()

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