| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | imm-peephole-arm.mir | 4 # CHECK: [[SUM1TMP:%.*]]:rgpr = ADDri [[IN]], 133 5 # CHECK: [[SUM1:%.*]]:rgpr = ADDri killed [[SUM1TMP]], 25600 13 # CHECK: [[SUM4TMP:%.*]]:rgpr = ADDri killed [[IN]], 133 14 # CHECK: [[SUM4:%.*]]:rgpr = ADDri killed [[SUM4TMP]], 25600
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| H A D | store-prepostinc.mir | 46 renamable $r0 = nuw ADDri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg 67 renamable $r0 = nuw ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg 88 renamable $r0 = nuw ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg 109 renamable $r0 = nuw ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg 130 renamable $r0 = nuw ADDri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg 151 renamable $r0 = nuw ADDri killed renamable $r0, 4095, 14 /* CC::al */, $noreg, $noreg 172 renamable $r0 = nuw ADDri killed renamable $r0, 4096, 14 /* CC::al */, $noreg, $noreg 257 renamable $r0 = nuw ADDri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg 277 renamable $r0 = nuw ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg 297 renamable $r0 = nuw ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg [all …]
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| H A D | no-register-coalescing-in-returnsTwice.mir | 10 # CHECK: %[[R1:[0-9]+]]:gpr = ADDri %stack.0.P0, 0, 14 13 # CHECK: %[[R2:[0-9]+]]:gpr = nuw ADDri %[[R1]], 8, 14 97 %1:gpr = ADDri %stack.0.P0, 0, 14, $noreg, $noreg 98 %2:gpr = ADDri %1, 40, 14, $noreg, $noreg 100 %3:gpr = ADDri %1, 24, 14, $noreg, $noreg 102 %4:gpr = nuw ADDri %1, 8, 14, $noreg, $noreg 107 %6:gpr = ADDri %stack.1.jb1, 0, 14, $noreg, $noreg 139 %28:gpr = ADDri %stack.1.jb1, 0, 14, $noreg, $noreg 149 %11:gpr = ADDri killed %1, 52, 14, $noreg, $noreg 156 %14:gpr = ADDri %stack.1.jb1, 0, 14, $noreg, $noreg [all …]
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| H A D | crash-O0.ll | 17 ; This function uses the scavenger for an ADDri instruction.
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| H A D | machine-outliner-thunk.ll | 24 ; ARM-NEXT: renamable $r0 = ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg 66 ; ARM-NEXT: renamable $r0 = ADDri killed renamable $r0, 88, 14 /* CC::al */, $noreg, $noreg
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| H A D | fp16-litpool2-arm.mir | 105 $sp = ADDri $sp, 4, 14, $noreg, $noreg
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| H A D | register-scavenger-exceptions.mir | 45 ; CHECK: $r11 = frame-setup ADDri killed $sp, 8, 14 /* CC::al */, $noreg, $noreg
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| H A D | fp16-litpool3-arm.mir | 111 $sp = ADDri $sp, 4, 14, $noreg, $noreg
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| H A D | fp16-litpool-arm.mir | 88 $sp = ADDri $sp, 4, 14, $noreg, $noreg
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcFrameLowering.cpp | 45 unsigned ADDri) const { in emitSPAdjustment() 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment() 115 SAVEri = SP::ADDri; in emitPrologue() 179 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased) in emitPrologue() 192 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6) in emitPrologue() 208 emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri); in eliminateCallFramePseudoInstr() 233 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri); in emitEpilogue()
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| H A D | SparcFrameLowering.h | 62 int NumBytes, unsigned ADDrr, unsigned ADDri) const;
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| H A D | DelaySlotFiller.cpp | 507 case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break; in tryCombineRestoreWithPrevInst()
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| H A D | SparcInstrAliases.td | 386 def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>; 389 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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| /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/ARM/ |
| H A D | dbgcall-site-interpretation.mir | 140 $r11 = frame-setup ADDri $sp, 8, 14, $noreg, $noreg 147 renamable $r0 = nsw ADDri killed $r0, 2, 14, $noreg, $noreg, debug-location !22 150 renamable $r2 = ADDri $sp, 4, 14, $noreg, $noreg 157 renamable $r1 = nsw ADDri killed renamable $r4, 8, 14, $noreg, $noreg, debug-location !22
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| H A D | dbgcallsite-noreg-is-imm-check.mir | 68 $r11 = frame-setup ADDri $sp, 8, 14, $noreg, $noreg
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| H A D | live-debug-values-reg-copy.mir | 134 renamable $r4 = ADDri killed renamable $r0, 10, 14, $noreg, $noreg, debug-location !16
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| H A D | dbgcall-site-propagated-value.mir | 153 $r11 = frame-setup ADDri $sp, 8, 14, $noreg, $noreg
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | README.txt | 35 %reg1037 = ADDri %reg1039, 1 43 Note ADDri is not a two-address instruction. However, its result %reg1037 is an 45 PHI node. We should treat it as a two-address code and make sure the ADDri is
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| /llvm-project-15.0.7/llvm/test/CodeGen/MIR/ARM/ |
| H A D | cfi-same-value.mir | 77 $sp = ADDri killed $sp, 40, 14, _, _
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/ |
| H A D | arm-instruction-select.mir | 590 ; CHECK: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 255, 14 /* CC::al */, $noreg, $noreg 591 ; CHECK: $r0 = COPY [[ADDri]] 937 ; CHECK: [[ADDri:%[0-9]+]]:gpr = ADDri %fixed-stack.0, 0, 14 /* CC::al */, $noreg, $noreg 938 ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 [[ADDri]], 0, 14 /* CC::al */, $noreg :: (load (s32)) 940 ; CHECK: [[ADDri1:%[0-9]+]]:gpr = ADDri %fixed-stack.2, 0, 14 /* CC::al */, $noreg, $noreg
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMMCInstLower.cpp | 139 case ARM::ADDri: in LowerARMMachineInstrToMCInst()
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| H A D | ARMInstructionSelector.cpp | 107 unsigned ADDri; member 320 STORE_OPCODE(ADDri, ADDri); in OpcodeCache() 1073 I.setDesc(TII.get(Opcodes.ADDri)); in select()
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| H A D | ARMBaseInstrInfo.cpp | 227 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress() 258 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress() 2432 {ARM::ADDSri, ARM::ADDri}, 2507 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate() 2652 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex() 2910 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) && in isRedundantFlagInstr() 2962 case ARM::ADDri: in isOptimizeCompareCandidate() 3361 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri; in FoldImmediate() 3364 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri; in FoldImmediate() 4936 unsigned AddOpc = (LoadImmOpc == ARM::MRC) ? ARM::ADDri : ARM::t2ADDri; in expandLoadStackGuardBase() [all …]
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| H A D | ARMAsmPrinter.cpp | 1245 case ARM::ADDri: in EmitUnwindingInstruction() 2018 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in emitInstruction() 2045 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in emitInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 731 const MCInstrDesc &ADDri = in processInstructionForSlowLEA() local 734 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), ADDri, DstR) in processInstructionForSlowLEA()
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