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Searched refs:ADDlow (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h65 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand. enumerator
H A DAArch64ISelDAGToDAG.cpp1020 if (N.getOpcode() == AArch64ISD::ADDlow && isWorthFoldingADDlow(N)) { in SelectAddrModeIndexed()
3003 if (LN->getOperand(1).getOpcode() != AArch64ISD::ADDlow || in SelectCVTFixedPosOperand()
H A DAArch64ISelLowering.cpp1920 case AArch64ISD::ADDlow: { in computeKnownBitsForTargetNode()
2049 MAKE_CASE(AArch64ISD::ADDlow) in getTargetNodeName()
7156 return DAG.getNode(AArch64ISD::ADDlow, DL, Ty, ADRP, Lo); in getAddr()
7519 DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, TLSIndexLo); in LowerWindowsGlobalTLSAddress()
7546 Addr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, Addr, TGALo); in LowerWindowsGlobalTLSAddress()
H A DAArch64InstrInfo.td513 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;