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Searched refs:ADDSUB (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h342 X86_INTRINSIC_DATA(avx_addsub_pd_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
343 X86_INTRINSIC_DATA(avx_addsub_ps_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
1314 X86_INTRINSIC_DATA(sse3_addsub_pd, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
1315 X86_INTRINSIC_DATA(sse3_addsub_ps, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
H A DX86ISelLowering.h213 ADDSUB, enumerator
H A DX86InstrFragmentsSIMD.td510 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
H A DX86ISelLowering.cpp10374 return DAG.getNode(X86ISD::ADDSUB, DL, VT, Opnd0, Opnd1); in lowerToAddSubOrFMAddSub()
33720 NODE_NAME_CASE(ADDSUB) in getTargetNodeName()
40693 return DAG.getNode(X86ISD::ADDSUB, DL, VT, Opnd0, Opnd1); in combineShuffleToAddSubOrFMAddSub()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dsse3-avx-addsub.ll6 ; Test ADDSUB ISel patterns.
H A Dfmaddsub-combine.ll7 ; This test checks the fusing of MUL + ADDSUB to FMADDSUB.
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td2471 // SVE2 ADDSUB Long Unpredicated.