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Searched refs:ADDS (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dnegative-immediates.s57 ADDS r0, r1, #0xFFFFFF00
60 # CHECK-DISABLED: ADDS
61 ADDS.W r0, r1, #0xFFFFFF00
64 # CHECK-DISABLED: ADDS.W
H A Dthumb2-narrow-dp.ll15 ADDS r0, r0, #5 // T1
17 ADDS r1, r1, #8 // T2
19 ADDS.W r1, r1, #8 // .w => T3
21 ADDS r8, r8, #8 // T3
43 ADDS r0, r2, r1 // ADDS has T1 narrow 3 operand
45 ADDS r2, r2, r1 // ADDS has T1 narrow 3 operand
H A Dbasic-arm-instructions.s302 @ ADDS
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Doptionaldef-scheduling.ll6 ; a flag-setting instruction in between an ADDS and the corresponding ADC.
H A Dlong.ll136 define i64 @f9d(i64 %x, i32 %y) { ; SUBS with small negative imm => ADDS imm
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-pred-arith.ll4 ; LEGAL ADDS
47 ; ILLEGAL ADDS
H A Dcond-br-tuning.ll7 ; CMN is an alias of ADDS.
H A Daddsub.ll409 ; ADDS and SUBS Optimizations
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-aliases.s58 ; ADDS to WZR/XZR is a CMN
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM7.td326 (instregex "t2(ADC|ADDS|ADD|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|SUBS)rs$",
H A DARMInstrInfo.td3835 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3840 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3844 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX2T99.td426 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
448 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
467 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
H A DAArch64SchedThunderX3T110.td685 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
707 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
726 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
H A DAArch64ISelLowering.h138 ADDS, enumerator
H A DAArch64SchedKryoDetails.td357 (instregex "ADDS?(W|X)ri")>;
363 (instregex "ADDS?(W|X)r(r|s|x)(64)?")>;
H A DAArch64SchedA64FX.td820 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
841 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
859 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
H A DAArch64ISelLowering.cpp2098 MAKE_CASE(AArch64ISD::ADDS) in getTargetNodeName()
2908 Opcode = AArch64ISD::ADDS; in emitComparison()
2913 Opcode = AArch64ISD::ADDS; in emitComparison()
3403 Opc = AArch64ISD::ADDS; in getAArch64XALUOOp()
3407 Opc = AArch64ISD::ADDS; in getAArch64XALUOOp()
18209 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS) in performBRCONDCombine()
H A DAArch64InstrInfo.td558 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
1691 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dopt-fold-compare.mir27 # Tests whose names start with cmn_ should use ADDS for the G_ICMP. Tests whose
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dbasic-arm-instructions.txt178 # ADDS