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/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Demergency-slot.mir180 renamable $x1 = ADDI $x0, 255
182 renamable $x6 = ADDI %stack.0, 384
184 renamable $x10 = ADDI $x0, 128
188 renamable $x18 = ADDI %stack.0, 1152
189 renamable $x19 = ADDI %stack.0, 1280
195 renamable $x25 = ADDI %stack.0, 0
196 renamable $x26 = ADDI %stack.0, 0
197 renamable $x27 = ADDI $x0, 2
198 renamable $x28 = ADDI %stack.0, 640
199 renamable $x29 = ADDI %stack.0, 768
[all …]
H A Daddi-scalable-offset.mir31 ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -2032
37 ; CHECK-NEXT: $x8 = frame-setup ADDI $x2, 2032
39 ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -240
52 ; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2048
53 ; CHECK-NEXT: $x2 = frame-destroy ADDI killed $x2, -224
54 ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 240
57 ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032
62 %3:gpr = ADDI %stack.2, 0
H A Dzvlsseg-spill.mir24 ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -16
31 ; CHECK-NEXT: $x11 = ADDI $x2, 16
34 ; CHECK-NEXT: $x11 = ADDI $x2, 16
41 ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16
H A Dframeindex-addr.ll19 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.a, 0
20 ; CHECK-NEXT: PseudoVSE64_V_M1 [[COPY]], killed [[ADDI]], 1, 6 /* e64 */
H A Drvv-stack-align.mir188 $x10 = ADDI %stack.0.a, 0
189 $x11 = ADDI %stack.1.b, 0
190 $x12 = ADDI %stack.2.c, 0
233 $x10 = ADDI %stack.0.a, 0
234 $x11 = ADDI %stack.1.b, 0
235 $x12 = ADDI %stack.2.c, 0
278 $x10 = ADDI %stack.0.a, 0
279 $x11 = ADDI %stack.1.b, 0
280 $x12 = ADDI %stack.2.c, 0
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dvector-abi.ll14 ; RV32: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
15 ; RV32: SW killed [[ADDI]], %stack.0, 12 :: (store (s32) into %stack.0)
16 ; RV32: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
18 ; RV32: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
20 ; RV32: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
22 ; RV32: [[ADDI4:%[0-9]+]]:gpr = ADDI %stack.0, 0
34 ; RV64: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
36 ; RV64: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
38 ; RV64: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
40 ; RV64: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
[all …]
H A Dmake-compressible-rv64.mir143 renamable $x10 = ADDI $x0, 1
145 renamable $x10 = ADDI $x0, 3
147 renamable $x10 = ADDI $x0, 5
169 renamable $x10 = ADDI $x0, 1
171 renamable $x10 = ADDI $x0, 3
218 renamable $x11 = ADDI $x0, 1
220 renamable $x11 = ADDI $x0, 3
222 renamable $x11 = ADDI $x0, 5
224 renamable $x11 = ADDI $x0, 7
281 renamable $x10 = ADDI $x0, 1
[all …]
H A Dmachineoutliner-jumptable.mir25 ; RV32I-MO: $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
30 ; RV64I-MO: $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
33 $x12 = ADDI $x10, 17
37 $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
44 $x12 = ADDI $x10, 17
48 $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
55 $x12 = ADDI $x10, 17
59 $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
H A Dselect-optimize-multiple.mir67 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
95 ; RV32IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
123 ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
151 ; RV64IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
168 %8:gpr = ADDI %7, 1
213 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
214 ; RV32I-NEXT: DBG_VALUE [[ADDI]], $noreg
237 ; RV32IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
261 ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
285 ; RV64IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
[all …]
H A Dmake-compressible-for-store-address.mir33 ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
34 ; CHECK-NEXT: $x12 = ADDI $x10, 768
37 ; CHECK-NEXT: renamable $x11 = ADDI $x0, 2
40 renamable $x11 = ADDI $x0, 1
43 renamable $x11 = ADDI $x0, 2
H A Dmake-compressible.mir409 renamable $x10 = ADDI $x0, 1
411 renamable $x10 = ADDI $x0, 3
413 renamable $x10 = ADDI $x0, 5
445 renamable $x10 = ADDI $x0, 1
447 renamable $x10 = ADDI $x0, 3
629 renamable $x11 = ADDI $x0, 1
631 renamable $x11 = ADDI $x0, 3
633 renamable $x11 = ADDI $x0, 5
635 renamable $x11 = ADDI $x0, 7
874 renamable $x10 = ADDI $x0, 1
[all …]
H A Dmachineoutliner.mir36 $x12 = ADDI $x10, 17
54 $x12 = ADDI $x10, 17
72 $x12 = ADDI $x10, 17
90 $x12 = ADDI $x10, 17
108 $x12 = ADDI $x10, 17
126 $x12 = ADDI $x10, 17
H A Dcopy-frameindex.mir51 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0, 0
52 ; CHECK-NEXT: SW $x0, killed [[ADDI]], 0 :: (volatile store (s32) into %stack.0)
60 %1:gpr = ADDI %stack.0, 0
H A Dverify-instr.mir4 # CHECK: - instruction: $x2 = ADDI $x1, 10000
10 $x2 = ADDI $x1, 10000
H A Dearly-clobber-tied-def-subreg-liveness.mir140 ; CHECK-NEXT: 32B %1:gpr = ADDI %0:gpr, target-flags(riscv-lo) @__const._Z3foov.var_49
144 ; CHECK-NEXT: 96B %4:gpr = ADDI %3:gpr, target-flags(riscv-lo) @__const._Z3foov.var_48
147 ; CHECK-NEXT: 144B %7:gpr = ADDI %6:gpr, target-flags(riscv-lo) @__const._Z3foov.var_46
169 ; CHECK-NEXT: 496B %27:gpr = ADDI %26:gpr, target-flags(riscv-lo) @var_47
173 %1:gpr = ADDI %0, target-flags(riscv-lo) @__const._Z3foov.var_49
177 %4:gpr = ADDI %3, target-flags(riscv-lo) @__const._Z3foov.var_48
180 %7:gpr = ADDI %6, target-flags(riscv-lo) @__const._Z3foov.var_46
183 %10:gpr = ADDI %9, target-flags(riscv-lo) @__const._Z3foov.var_45
187 %13:gpr = ADDI %12, target-flags(riscv-lo) @__const._Z3foov.var_44
192 %17:gpr = ADDI %16, target-flags(riscv-lo) @__const._Z3foov.var_40
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-reduce/mir/
H A Dinstr-reduce.mir7 # interestingness-test 'instr-reduce.py' matches a '%[0-9]+:gpr = ADDI %[0-9]+, 5'
12 # CHECK-NEXT: %{{[0-9]+}}:gpr = ADDI [[IMPDEF]], 5
24 %20:gpr = ADDI %10, 1
25 %30:gpr = ADDI %20, 5
26 %40:gpr = ADDI %30, 9
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dctrloops32.mir15 ; CHECK-NOT: ADDI
40 ; CHECK: ADDI
66 ; CHECK: ADDI
92 ; CHECK: ADDI
119 ; CHECK-NOT: ADDI
144 ; CHECK: ADDI
171 ; CHECK: ADDI
201 ; CHECK: ADDI
227 ; CHECK: ADDI
278 ; CHECK: ADDI
[all …]
H A Dpeephole-subreg-def.mir28 ; CHECK: [[ADDI:%[0-9]+]]:gprc = ADDI killed [[COPY2]], 1
29 ; CHECK: [[EXTSW_32_64_:%[0-9]+]]:g8rc_and_g8rc_nox0 = EXTSW_32_64 killed [[ADDI]]
37 %5:gprc = ADDI killed %4, 1
H A Dexpand-isel-8.mir46 $r4 = ADDI $r3, 1
58 ; CHECK: $r5 = ADDI $r3, 0
59 ; CHECK: $r3 = ADDI $r4, 0
60 ; CHECK: $r4 = ADDI $r3, 0
H A Daix32-vector-vararg-fixed-callee.ll13 ; CHECK: [[ADDI:%[0-9]+]]:gprc = ADDI %fixed-stack.0, 0
14 ; CHECK: STW killed [[ADDI]], 0, %stack.0.arg_list :: (store (s32) into %ir.0)
15 ; CHECK: [[ADDI1:%[0-9]+]]:gprc = ADDI %fixed-stack.0, 15
H A Daix32-vector-vararg-callee.ll26 ; CHECK: [[ADDI:%[0-9]+]]:gprc = ADDI %fixed-stack.0, 0
27 ; CHECK: STW killed [[ADDI]], 0, %stack.0.arg_list :: (store (s32) into %ir.0)
28 ; CHECK: [[ADDI1:%[0-9]+]]:gprc = ADDI %fixed-stack.0, 15
H A Dfold-frame-offset-using-rr.mir3 # ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, OffsetAddi
9 # new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, (OffsetAddi + OffsetImm)
65 # There is other use for ToBeChangedReg between ADDI instr and ADD instr
H A Dconvert-rr-to-ri-p9-vector.mir37 %3 = ADDI %2, 1
43 %8 = ADDI %2, 2
84 %3 = ADDI %2, 1
90 %8 = ADDI %2, 2
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp47 bool detectLuiAddiGlobal(MachineInstr &LUI, MachineInstr *&ADDI);
102 if (LoADDI->getOpcode() != RISCV::ADDI || in INITIALIZE_PASS()
159 if (OffsetTail.getOpcode() == RISCV::ADDI || in matchLargeOffset()
226 if (OffsetTail.getOpcode() != RISCV::ADDI) in matchShiftedOffset()
266 case RISCV::ADDI: { in detectAndFoldOffset()
274 if (TailTail.getOpcode() == RISCV::ADDI) { in detectAndFoldOffset()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp28 case RISCV::ADDI: in getInstSeqCost()
68 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
154 Res.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12)); in generateInstSeqImpl()
359 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12)); in generateInstSeq()
373 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDI, NegImm12)); in generateInstSeq()
410 case RISCV::ADDI: in getOpndKind()

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