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Searched refs:ADCS (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcopy-cpsr.ll6 ; escape. However, for long ADCS chains (and last ditch fallback) the dependency
12 ; + We want 2 long ADCS chains
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dnzcv-save.ll4 ; DAG ends up with two uses for the flags from an ADCS node, which means they
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb2-narrow-dp.ll488 ADCS r5, r5, r1 // Should choose narrow
489 ADCS r3, r1, r3 // Should choose narrow - commutative
490 ADCS.W r2, r2, r1 // Explicitly wide
491 ADCS.W r3, r1, r3
493 ADCS r7, r7, r1 // Should use narrow
494 ADCS r7, r1, r7 // Commutative
496 ADCS r8, r8, r1
497 ADCS r5, r8, r5
498 ADCS r2, r2, r8
499 ADCS r3, r3, r1, lsl #1 // Must use wide - shifted register
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h140 ADCS, enumerator
H A DAArch64ISelLowering.cpp2100 MAKE_CASE(AArch64ISD::ADCS) in getTargetNodeName()
5395 return lowerADDSUBCARRY(Op, DAG, AArch64ISD::ADCS, false /*unsigned*/); in LowerOperation()
5399 return lowerADDSUBCARRY(Op, DAG, AArch64ISD::ADCS, true /*signed*/); in LowerOperation()
19512 case AArch64ISD::ADCS: in PerformDAGCombine()
H A DAArch64InstrInfo.td563 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;