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Searched refs:AArch64InstrInfo (Results 1 – 25 of 28) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64MachineScheduler.cpp29 return AArch64InstrInfo::getLdStOffsetOp(*MI).isImm(); in needReorderStoreMI()
38 const MachineOperand &Base0 = AArch64InstrInfo::getLdStBaseOp(MI0); in mayOverlapWrite()
39 const MachineOperand &Base1 = AArch64InstrInfo::getLdStBaseOp(MI1); in mayOverlapWrite()
45 int StoreSize0 = AArch64InstrInfo::getMemScale(MI0); in mayOverlapWrite()
46 int StoreSize1 = AArch64InstrInfo::getMemScale(MI1); in mayOverlapWrite()
47 Off0 = AArch64InstrInfo::hasUnscaledLdStOffset(MI0.getOpcode()) in mayOverlapWrite()
48 ? AArch64InstrInfo::getLdStOffsetOp(MI0).getImm() in mayOverlapWrite()
50 Off1 = AArch64InstrInfo::hasUnscaledLdStOffset(MI1.getOpcode()) in mayOverlapWrite()
51 ? AArch64InstrInfo::getLdStOffsetOp(MI1).getImm() in mayOverlapWrite()
55 int Multiples = AArch64InstrInfo::isPairedLdSt(MI) ? 2 : 1; in mayOverlapWrite()
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H A DAArch64LoadStoreOptimizer.cpp124 const AArch64InstrInfo *TII;
593 bool IsPaired = AArch64InstrInfo::isPairedLdSt(MI); in getPrePostIndexedMemOpInfo()
612 bool IsPreLdSt = AArch64InstrInfo::isPreLdSt(MI); in getLdStRegOp()
712 if (!AArch64InstrInfo::getLdStOffsetOp(MI).isImm()) in isMergeableLdStUpdate()
751 if (AArch64InstrInfo::getLdStOffsetOp(*I).getImm() == in mergeNarrowZeroStores()
948 !AArch64InstrInfo::isPreLdSt(*I)) { in mergePairedInsns()
998 if (AArch64InstrInfo::isPreLdSt(*RtMI)) in mergePairedInsns()
1297 return !AArch64InstrInfo::isPreLdSt(FirstMI); in areCandidatesToMergeOrPair()
1805 if (!AArch64InstrInfo::isPairedLdSt(*I)) { in mergeUpdateInsn()
1810 .add(AArch64InstrInfo::getLdStBaseOp(*I)) in mergeUpdateInsn()
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H A DAArch64MacroFusion.cpp63 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticBccPair()
113 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticCbzPair()
250 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isCCSelectPair()
252 return !AArch64InstrInfo::hasExtendedReg(*FirstMI); in isCCSelectPair()
268 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isCCSelectPair()
271 return !AArch64InstrInfo::hasExtendedReg(*FirstMI); in isCCSelectPair()
284 if (AArch64InstrInfo::hasShiftedReg(SecondMI)) in isArithmeticLogicPair()
345 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticLogicPair()
373 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticLogicPair()
H A DAArch64InstrInfo.cpp71 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI) in AArch64InstrInfo() function in AArch64InstrInfo
476 void AArch64InstrInfo::instantiateCondBranch( in instantiateCondBranch()
493 unsigned AArch64InstrInfo::insertBranch( in insertBranch()
1292 bool AArch64InstrInfo::optimizePTestInstr( in optimizePTestInstr()
1422 bool AArch64InstrInfo::optimizeCompareInstr( in optimizeCompareInstr()
1682 bool AArch64InstrInfo::substituteCmpToZero( in substituteCmpToZero()
3177 AArch64InstrInfo::isPairedLdSt(MI) || AArch64InstrInfo::isPreLdSt(MI) ? 2 in getLdStBaseOp()
3185 AArch64InstrInfo::isPairedLdSt(MI) || AArch64InstrInfo::isPreLdSt(MI) ? 3 in getLdStOffsetOp()
3298 bool AArch64InstrInfo::shouldClusterMemOps( in shouldClusterMemOps()
4729 MCInst AArch64InstrInfo::getNop() const { in getNop()
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H A DAArch64BranchTargets.cpp112 const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>( in addBTI()
H A DAArch64StorePairSuppress.cpp31 const AArch64InstrInfo *TII;
126 TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo()); in runOnMachineFunction()
H A DAArch64Subtarget.h126 AArch64InstrInfo InstrInfo;
171 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
H A DAArch64Schedule.td13 const AArch64InstrInfo *TII =
14 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo());
H A DAArch64CondBrTuning.cpp48 const AArch64InstrInfo *TII;
288 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
H A DAArch64InstrInfo.h37 class AArch64InstrInfo final : public AArch64GenInstrInfo {
42 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
431 const AArch64InstrInfo *TII);
H A DAArch64StackTaggingPreRA.cpp64 const AArch64InstrInfo *TII;
343 TII = static_cast<const AArch64InstrInfo *>(MF->getSubtarget().getInstrInfo()); in runOnMachineFunction()
H A DAArch64RegisterInfo.cpp618 const AArch64InstrInfo *TII = in materializeFrameBaseRegister()
646 const AArch64InstrInfo *TII = in resolveFrameIndex()
658 const AArch64InstrInfo *TII) { in createScratchRegisterForInstruction()
718 const AArch64InstrInfo *TII = in eliminateFrameIndex()
H A DCMakeLists.txt64 AArch64InstrInfo.cpp
H A DAArch64MIPeepholeOpt.cpp58 const AArch64InstrInfo *TII;
481 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
H A DAArch64SchedPredicates.td65 "AArch64InstrInfo::isFpOrNEON"
71 "AArch64InstrInfo::isQForm"
H A DAArch64LowerHomogeneousPrologEpilog.cpp45 const AArch64InstrInfo *TII;
604 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
H A DAArch64FrameLowering.cpp469 const AArch64InstrInfo *TII = in eliminateCallFramePseudoInstr()
470 static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in eliminateCallFramePseudoInstr()
789 const AArch64InstrInfo &TII = *STI.getInstrInfo(); in emitZeroCallUsedRegs()
1170 if (AArch64InstrInfo::isSEHInstruction(*SEH)) in convertCalleeSaveRestoreToSPPrePostIncDec()
1177 bool Success = static_cast<const AArch64InstrInfo *>(TII)->getMemOpInfo( in convertCalleeSaveRestoreToSPPrePostIncDec()
1238 if (AArch64InstrInfo::isSEHInstruction(MI)) in fixupCalleeSaveRestoreStackOffset()
1277 assert(AArch64InstrInfo::isSEHInstruction(*MBBI) && in fixupCalleeSaveRestoreStackOffset()
1972 AArch64InstrInfo::isSEHInstruction(*Pop)) in emitEpilogue()
3404 const AArch64InstrInfo *TII = in emitUnrolled()
3446 const AArch64InstrInfo *TII = in emitLoop()
H A DAArch64SIMDInstrOpt.cpp701 const AArch64InstrInfo *AAII = in runOnMachineFunction()
702 static_cast<const AArch64InstrInfo *>(ST.getInstrInfo()); in runOnMachineFunction()
H A DAArch64FalkorHWPFFix.cpp206 const AArch64InstrInfo *TII;
823 TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo()); in runOnMachineFunction()
H A DAArch64.td579 include "AArch64InstrInfo.td"
585 def AArch64InstrInfo : InstrInfo;
1281 let InstructionSet = AArch64InstrInfo;
/llvm-project-15.0.7/llvm/unittests/Target/AArch64/
H A DInstSizes.cpp36 return std::make_unique<AArch64InstrInfo>(ST); in createInstrInfo()
128 [](AArch64InstrInfo &II, MachineFunction &MF) { in TEST()
143 [](AArch64InstrInfo &II, MachineFunction &MF) { in TEST()
158 [](AArch64InstrInfo &II, MachineFunction &MF) { in TEST()
171 [](AArch64InstrInfo &II, MachineFunction &MF) { in TEST()
187 [](AArch64InstrInfo &II, MachineFunction &MF) { in TEST()
201 [](AArch64InstrInfo &II, MachineFunction &MF) { in TEST()
215 [](AArch64InstrInfo &II, MachineFunction &MF) { in TEST()
229 [](AArch64InstrInfo &II, MachineFunction &MF) { in TEST()
243 [](AArch64InstrInfo &II, MachineFunction &MF) { in TEST()
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H A DDecomposeStackOffsetTest.cpp23 AArch64InstrInfo::decomposeStackOffsetForFrameOffsets(A + B + C, ByteSized, PLSized, in TEST()
32 AArch64InstrInfo::decomposeStackOffsetForFrameOffsets(C + D, ByteSized, PLSized, VLSized); in TEST()
39 AArch64InstrInfo::decomposeStackOffsetForFrameOffsets(E + F, ByteSized, PLSized, VLSized); in TEST()
49 AArch64InstrInfo::decomposeStackOffsetForFrameOffsets(G + H, ByteSized, PLSized, VLSized); in TEST()
H A DMatrixRegisterAliasing.cpp27 std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) { in createInstrInfo()
32 return std::make_unique<AArch64InstrInfo>(ST); in createInstrInfo()
38 std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get()); in TEST()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Doptimize-cond-branch.ll5 ; AArch64InstrInfo::optimizeCondBranch() optimizes the
/llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/
H A DBUILD.gn128 "AArch64InstrInfo.cpp",

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