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Searched refs:xe_mmio_write32 (Results 1 – 25 of 25) sorted by relevance

/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_irq.c49 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
51 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
69 xe_mmio_write32(mmio, IER(irqregs), bits); in unmask_and_enable()
70 xe_mmio_write32(mmio, IMR(irqregs), ~bits); in unmask_and_enable()
81 xe_mmio_write32(mmio, IMR(irqregs), ~0); in mask_and_disable()
85 xe_mmio_write32(mmio, IER(irqregs), 0); in mask_and_disable()
88 xe_mmio_write32(mmio, IIR(irqregs), ~0); in mask_and_disable()
90 xe_mmio_write32(mmio, IIR(irqregs), ~0); in mask_and_disable()
98 xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0); in xelp_intr_disable()
401 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0); in dg1_intr_disable()
[all …]
H A Dxe_gt_idle.c141 xe_mmio_write32(mmio, MEDIA_POWERGATE_IDLE_HYSTERESIS, 25); in xe_gt_idle_enable_pg()
142 xe_mmio_write32(mmio, RENDER_POWERGATE_IDLE_HYSTERESIS, 25); in xe_gt_idle_enable_pg()
145 xe_mmio_write32(mmio, POWERGATE_ENABLE, gtidle->powergate_enable); in xe_gt_idle_enable_pg()
161 xe_mmio_write32(&gt->mmio, POWERGATE_ENABLE, gtidle->powergate_enable); in xe_gt_idle_disable_pg()
383 xe_mmio_write32(&gt->mmio, RC_IDLE_HYSTERSIS, 0x3B9ACA); in xe_gt_idle_enable_c6()
385 xe_mmio_write32(&gt->mmio, RC_CONTROL, in xe_gt_idle_enable_c6()
397 xe_mmio_write32(&gt->mmio, RC_CONTROL, 0); in xe_gt_idle_disable_c6()
398 xe_mmio_write32(&gt->mmio, RC_STATE, 0); in xe_gt_idle_disable_c6()
H A Dxe_gt_sriov_pf.c108 xe_mmio_write32(&gt->mmio, VIRTUAL_CTRL_REG, GUEST_GTT_UPDATE_EN); in pf_enable_ggtt_guest_update()
150 xe_mmio_write32(&gt->mmio, scratch, 0); in pf_clear_vf_scratch_regs()
156 xe_mmio_write32(&gt->mmio, scratch, 0); in pf_clear_vf_scratch_regs()
H A Dxe_gt_mcr.c532 xe_mmio_write32(&gt->mmio, MCFG_MCR_SELECTOR, steer_val); in xe_gt_mcr_set_implicit_defaults()
533 xe_mmio_write32(&gt->mmio, SF_MCR_SELECTOR, steer_val); in xe_gt_mcr_set_implicit_defaults()
627 xe_mmio_write32(&gt->mmio, STEER_SEMAPHORE, 0x1); in mcr_unlock()
674 xe_mmio_write32(mmio, steer_reg, steer_val); in rw_with_mcr_steering()
679 xe_mmio_write32(mmio, reg, value); in rw_with_mcr_steering()
688 xe_mmio_write32(mmio, steer_reg, MCR_MULTICAST); in rw_with_mcr_steering()
796 xe_mmio_write32(&gt->mmio, reg, value); in xe_gt_mcr_multicast_write()
H A Dxe_execlist.c64 xe_mmio_write32(mmio, RCU_MODE, in __start_lrc()
82 xe_mmio_write32(mmio, RING_HWS_PGA(hwe->mmio_base), in __start_lrc()
88 xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base), ring_mode); in __start_lrc()
90 xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base), in __start_lrc()
92 xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base), in __start_lrc()
94 xe_mmio_write32(mmio, RING_EXECLIST_CONTROL(hwe->mmio_base), in __start_lrc()
H A Dxe_guc.c279 xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(0), 0); in guc_write_params()
282 xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); in guc_write_params()
788 xe_mmio_write32(mmio, GDRST, GRDOM_GUC); in xe_guc_reset()
829 xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags); in guc_prepare_xfer()
831 xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
850 xe_mmio_write32(&gt->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); in guc_xfer_rsa()
859 xe_mmio_write32(&gt->mmio, UOS_RSA_SCRATCH(i), rsa[i]); in guc_xfer_rsa()
1184 xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(15), 0); in guc_handle_mmio_msg()
1201 xe_mmio_write32(&gt->mmio, GUC_SG_INTR_ENABLE, in guc_enable_irq()
1304 xe_mmio_write32(mmio, MED_VF_SW_FLAG(i), in xe_guc_mmio_send_recv()
[all …]
H A Dxe_pcode.c70 xe_mmio_write32(mmio, PCODE_DATA0, *data0); in __pcode_mailbox_rw()
71 xe_mmio_write32(mmio, PCODE_DATA1, data1 ? *data1 : 0); in __pcode_mailbox_rw()
72 xe_mmio_write32(mmio, PCODE_MAILBOX, PCODE_READY | mbox); in __pcode_mailbox_rw()
H A Dxe_mmio.c201 void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val) in xe_mmio_write32() function
237 xe_mmio_write32(mmio, reg, reg_val); in xe_mmio_rmw32()
247 xe_mmio_write32(mmio, reg, val); in xe_mmio_write32_and_verify()
H A Dxe_uc_fw.c820 xe_mmio_write32(mmio, DMA_ADDR_0_LOW, lower_32_bits(src_offset)); in uc_fw_xfer()
821 xe_mmio_write32(mmio, DMA_ADDR_0_HIGH, in uc_fw_xfer()
825 xe_mmio_write32(mmio, DMA_ADDR_1_LOW, offset); in uc_fw_xfer()
826 xe_mmio_write32(mmio, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); in uc_fw_xfer()
832 xe_mmio_write32(mmio, DMA_COPY_SIZE, in uc_fw_xfer()
836 xe_mmio_write32(mmio, DMA_CTRL, in uc_fw_xfer()
847 xe_mmio_write32(mmio, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags)); in uc_fw_xfer()
H A Dxe_gt_tlb_invalidation.c311 xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1, in xe_gt_tlb_invalidation_ggtt()
313 xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0, in xe_gt_tlb_invalidation_ggtt()
316 xe_mmio_write32(mmio, GUC_TLB_INV_CR, in xe_gt_tlb_invalidation_ggtt()
H A Dxe_mmio.h21 void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);
H A Dxe_device.c546 xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS); in __xe_driver_flr()
567 xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS); in __xe_driver_flr()
972 xe_mmio_write32(xe_root_tile_mmio(xe), VF_CAP_REG, 0); in xe_device_wmb()
1015 xe_mmio_write32(&gt->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST); in xe_device_td_flush()
1046 xe_mmio_write32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1); in xe_device_l2_flush()
H A Dxe_hw_engine.c303 xe_mmio_write32(&hwe->gt->mmio, reg, val); in xe_hw_engine_mmio_write32()
333 xe_mmio_write32(&hwe->gt->mmio, RCU_MODE, in xe_hw_engine_enable_ring()
592 xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly); in adjust_idledly()
806 xe_mmio_write32(&gt->mmio, GUNIT_GSC_INTR_ENABLE, 0); in check_gsc_availability()
807 xe_mmio_write32(&gt->mmio, GUNIT_GSC_INTR_MASK, ~0); in check_gsc_availability()
H A Dxe_pat.c168 xe_mmio_write32(&gt->mmio, reg, table[i].value); in program_pat()
320 xe_mmio_write32(&gt->mmio, XE_REG(_PAT_ATS), xe2_pat_ats.value); in xe2lpm_program_pat()
323 xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe2_pat_pta.value); in xe2lpm_program_pat()
H A Dxe_oa.c388 xe_mmio_write32(&stream->gt->mmio, oaheadptr, in xe_oa_append_reports()
414 xe_mmio_write32(mmio, __oa_regs(stream)->oa_status, 0); in xe_oa_init_oa_buffer()
415 xe_mmio_write32(mmio, __oa_regs(stream)->oa_head_ptr, in xe_oa_init_oa_buffer()
422 xe_mmio_write32(mmio, __oa_regs(stream)->oa_buffer, oa_buf); in xe_oa_init_oa_buffer()
423 xe_mmio_write32(mmio, __oa_regs(stream)->oa_tail_ptr, in xe_oa_init_oa_buffer()
496 xe_mmio_write32(mmio, OA_TLB_INV_CR, 1); in xe_oa_disable()
785 xe_mmio_write32(&stream->gt->mmio, __oa_regs(stream)->oa_ctrl, in xe_oa_configure_oac_context()
826 xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug, in xe_oa_disable_metric_set()
1089 xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug, in xe_oa_enable_metric_set()
2530 xe_mmio_write32(&gt->mmio, u->regs.oa_ctrl, 0); in __xe_oa_init_oa_units()
[all …]
H A Dxe_gt_ccs_mode.c77 xe_mmio_write32(&gt->mmio, CCS_MODE, mode); in __xe_gt_apply_ccs_mode()
H A Dxe_reg_sr.c164 xe_mmio_write32(&gt->mmio, reg, val); in apply_one_mmio()
H A Dxe_mocs.c694 xe_mmio_write32(&gt->mmio, XELP_GLOBAL_MOCS(i), mocs); in __init_mocs_table()
734 xe_mmio_write32(&gt->mmio, XELP_LNCFCMOCS(i), l3cc); in init_l3cc_table()
H A Dxe_pxp.c159 xe_mmio_write32(&gt->mmio, KCR_GLOBAL_TERMINATE, 1); in pxp_terminate_hw()
335 xe_mmio_write32(&pxp->gt->mmio, KCR_INIT, val); in kcr_pxp_set_status()
H A Dxe_force_wake.c107 xe_mmio_write32(&gt->mmio, domain->reg_ctl, domain->mask | (wake ? domain->val : 0)); in __domain_ctl()
H A Dxe_guc_pc.c276 xe_mmio_write32(&gt->mmio, RP_CONTROL, state); in pc_set_manual_rp_ctrl()
288 xe_mmio_write32(&gt->mmio, RPNSWREQ, rpnswreq); in pc_set_cur_freq()
H A Dxe_lmtt.c196 xe_mmio_write32(&tile->mmio, in lmtt_setup_dir_ptr()
H A Dxe_ggtt.c124 xe_mmio_write32(mmio, GMD_ID, 0x0); in ggtt_update_access_counter()
H A Dxe_gt.c684 xe_mmio_write32(&gt->mmio, GDRST, GRDOM_FULL); in do_gt_reset()
/linux-6.15/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_uncore.h90 xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val); in intel_uncore_write()
155 xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val); in intel_uncore_write_fw()
171 xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val); in intel_uncore_write_notrace()