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Searched refs:xe_mmio_wait32 (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_uncore.h107 return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value, in intel_wait_for_register()
117 return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value, in intel_wait_for_register_fw()
137 return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value, in __intel_wait_for_register()
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_mmio.h28 int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
H A Dxe_device.c541 ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); in __xe_driver_flr()
552 ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); in __xe_driver_flr()
559 ret = xe_mmio_wait32(mmio, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS, in __xe_driver_flr()
1023 if (xe_mmio_wait32(&gt->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0, in xe_device_td_flush()
1048 if (xe_mmio_wait32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 500, NULL, true)) in xe_device_l2_flush()
H A Dxe_pcode.c74 err = xe_mmio_wait32(mmio, PCODE_MAILBOX, PCODE_READY, 0, in __pcode_mailbox_rw()
H A Dxe_force_wake.c118 ret = xe_mmio_wait32(&gt->mmio, domain->reg_ack, domain->val, wake ? domain->val : 0, in __domain_wait()
H A Dxe_huc.c271 ret = xe_mmio_wait32(&gt->mmio, huc_auth_modes[type].reg, huc_auth_modes[type].val, in xe_huc_auth()
H A Dxe_mmio.c384 int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us, in xe_mmio_wait32() function
H A Dxe_guc.c790 ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); in xe_guc_reset()
1316 ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, in xe_guc_mmio_send_recv()
1342 ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask, in xe_guc_mmio_send_recv()
H A Dxe_gsc_proxy.c79 return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE), in xe_gsc_wait_for_proxy_init_done()
H A Dxe_gt_mcr.c617 ret = xe_mmio_wait32(&gt->mmio, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL, in mcr_lock()
H A Dxe_gsc.c194 return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE), in gsc_fw_wait()
H A Dxe_pxp.c129 return xe_mmio_wait32(&gt->mmio, KCR_SIP, mask, in_play ? mask : 0, in pxp_wait_for_session_state()
H A Dxe_gt.c685 err = xe_mmio_wait32(&gt->mmio, GDRST, GRDOM_FULL, 0, 5000, NULL, false); in do_gt_reset()
H A Dxe_uc_fw.c840 ret = xe_mmio_wait32(mmio, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl, in uc_fw_xfer()
H A Dxe_oa.c489 if (xe_mmio_wait32(mmio, __oa_regs(stream)->oa_ctrl, in xe_oa_disable()
497 if (xe_mmio_wait32(mmio, OA_TLB_INV_CR, 1, 0, 50000, NULL, false)) in xe_oa_disable()